10-BIT，5MS/S 低電壓管線式類比數位轉換器

A 10-BIT 5-MS/S LOW-VOLTAGE PIPELINE ADC

王偉仁(Wen-Ren wang)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2006年)

摘要

本篇論文中，我們設計了一個10位元5 Msample/s低電壓的管流式類比數位轉換器。因為電晶體臨界電壓不會隨製程變動，所以以往在管流式類比數位轉換器的電路在低電壓的情況下不能獲得足夠的動態範圍。因此，有些解決方法被提出以克服這個問題。在本篇論文中，是以運算放大器重設切換技巧來實現，我們並比較此方法與其他的解決方法的優缺點，並且分析了運算放大器的需求，已達到所需的精確度。

關鍵字

管線式類比數位轉換器 ； 低電壓

並列摘要

In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Several solutions have been proposed to overcome the problem. In this thesis, the pipeline ADC is design by opamp-reset switching technique. In addition, the comparison between different solutions has been made. We also analyze the operational amplifier requirement to meet the necessary accuracy.

並列關鍵字

pipeline ADC ； low voltage

參考文獻

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[2] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.

[3] S. H. Lewis, and P. R. Gray, “A Pipelined 5-Msample/s 9-bit analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. sc-22, pp. 954–961, Dec. 1987.

[4] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION, IEEE Press, 1997.

[5] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R.Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992.