12-BIT，50-MS/S內建類比式自我校正電路之管線式類比數位轉換器

A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC

沈游城(Yu-Chen Shen)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2006年)

摘要

本篇論文主要描述一個低功率、12位元、操作頻率在50MHz而工作電壓在3.3V的管流式類比數位轉換器之設計，並提出一個內建類比式自我校正電路架構以達到影像處理所需較低的微分、積分非線性特性。有別於一般的數位自我校正系統，本架構不需要龐大且複雜的數位電路，取而代之的是自我校正電容陣列與訊號線性區保護架構。本轉換器採用標準0.35um 2P4M CMOS製程，總功率消耗為148mW，佈局面積約為2.3mm×2.2mm，完整的測試報告將由日後提出。

關鍵字

管線式數位類比轉換器 ； 類比式自我校正電路

並列摘要

This thesis describes a design of a low-power, 12-bit, 50Msample/s, and 3.3-V supply pipeline analog-to-digital converter (ADC). In order to achieve the requirements of digital imaging, where differential nonlinearity (DNL) and integral nonlinearity (INL) are both important, we propose a built-in analog self-calibrated circuit of the ADC in this thesis. Compared with the ADC with the typical digital error correction architecture, our circuit does not need a large and complex digital circuit, but they are replaced by the self-calibration capacitor array and linear-range protection architecture. The entire circuit will be fabricated in a 0.35-um 2P4M CMOS process, the estimated chip area is 2.3×2.2mm2, and the power dissipation is 148mW. Final test results will be reported later.

並列關鍵字

Analog self-calibration circuit ； pipeline ADC

參考文獻

[1] I. E. Opris, L. D. Lewicki, and B. C. Wong, “A single-ended 12-bit 20Msample/s Self-Calibrating Pipeline A/D Converter,” IEEE Journal Solid-State Circuits, Vol. 33, pp. 1898-1903, Dec. 1998.

[4] I. E. Opris, B. C. Wong, and S. W. Chin, “A Pipeline A/D Converter Architecture with Low DNL,” IEEE Journal of Solid-State Circuits. Vol. 35, NO.2, Feb. 2000.

[5] Y. P. Lee and R. L. Geiger, “Gain Error Correction Scheme for Multiply-By-Two Gain Amplifier in Pipelined ADC,” IEEE International Solid-State Circuits Conference. Vol. 1, 8-11 Aug. 1999.

[6] M. Gustavsson, J. J. Wikner and N. N. Tan, CMOS Data Converters for Communications, Kluwer, 2000.

[7] K. M. Daugherty, Analog-to-Digital Conversion, McGraw-Hill, 1995.