採用無負載及放大器共享技術之8位元50MS/s之管線式類比數位轉換器

A 8-BIT 50MS/s PIPELINE ANALOG TO DIGITAL CONVERTER USING LOADING FREE AND OPAMP SHARING TECHNIQUES

賴偉修(Wei-Xiu Lai)

指導教授 ： 蔡明傑

大同大學/電機資訊學院/電機工程學系所/碩士(2009年)

摘要

本篇論文主要描述一個低功率、8位元、操作頻率在50MHz，而工作電壓在1.8V的管線式類比數位轉換器之設計，並利運算放大器共享技術以及無負載技術來減少轉換器元件數量，此法只要用到幾顆開關作切換，可以減少放大器以及電容的使用數量，也可以達到低消耗功率以及降低晶片面積的目的。另外，移去前端取樣保持電路也可以降低消耗功率。在講求節能省碳的現今社會，此方法很適合用來實現類比數位轉換器。本類比數位轉換器採用台積電0.18um 1P6M CMOS製程，使用Hspice模擬電路架構，操作在50MHz的取樣頻率下，工作電壓為1.8V，輸入頻率為1.123MHz下，SNDR為47.85.dB，其總功率消耗為82mW。

關鍵字

放大器共享 ； 無負載 ； 管線式 ； 8位元

並列摘要

This thesis describes A 8-bit 50M/s pipelined ADC with 1.8V supply voltage is designed and simulated with TSMC 0.18μm 1P6M CMOS models process. Many applications such as battery-powered or portable devices also require low power consumption. We proposed some method to reduce power consumption. In order to achieve a low-power pipelined ADC, we use opamp-sharing and loading-free architecture. An opamp with two output stages is employed to merge opamp-sharing and loading-free structures. We also remove sample-and-hold circuit to achieve low power consumption. We use a capacitance to replace sample-and-hold circuit. We reduce number of OPA and switches to achieve low power consumption. This ADC has been simulated by HSPICE. We implemented circuit in TSMC 0.18-μm 1P6M CMOS process. The simulation resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 47.85 dB. The total power consumption of this ADC is 82mW with 1.8V supply power. We verify this method to be able the effective reduce power consumption for low power system.

並列關鍵字

OPAMP SHARING ； PIPELINE ADC ； LOADING FREE ； 8bit

參考文獻

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