採用分段式電容陣列的12位元25MS/s 逐漸趨近式類比數位轉換器

一直以來逐漸趨近式類比數位轉換器操作速度會有所限制，原因在於電路中單位電容太大，導致電容陣列充電太慢，速度無法提升。本篇論文特別在架構中採用分段式電容陣列數位類比轉換器，目的在於降低SAR ADC的總取樣電容值，加快數位類比轉換器充電時間，同時也降低了電容開關所造成的功率消耗以及佈局所占面積。論文內容包含一個同架構的10-bit 20MS/s SAR ADC晶片量測結果，但最後結果不甚理想，經過電路的調整與精進，最後設計所定的規格為12-bit 25MS/s SAR ADC，於設計平台使用TSMC 0.18um 1P6M COMS製程，在電源供應1.8V的情況下，輸入頻率為1.214599609MHz進行前模擬，訊號雜訊與失真比SNDR為73.6465 dB，有效位元數ENOB為11.95 bits，功率消耗為1.7mW。品質因素FOM為17.51f J/conversion-step。晶片佈局面積為1.190mm×1.190mm，核心電路面積為0.56mm×0.32um，因佈局有訊號延遲的現象，導致取樣頻率最快只能以20MHz進行模擬，輸入頻率0.9716796875MHz進行後模擬，SNDR=49.4647dB，ENOB=7.92 bit。

關鍵字

逐漸趨近式；類比數位轉換器；低功耗；分段式電容陣列

並列摘要

The operating speed of SAR ADC has been limited, which is partly because the unit capacitance is too large, which causes the capacitor to charge too slowly and the speed cannot be improved. In this paper, a segmented capacitor array digital to analog converter is used in the architecture. The purpose is to reduce the total sampling capacitor value of the SAR ADC, to speed up the charging time of the digital analog converter, and also reduce the power consumption caused by the capacitor array and the area occupied by the layout. The content of the paper contains the measurement results of a 10-bit 20MS/s SAR ADC chip with the same architecture, but the final result is not very satisfactory. After the adjustment and refinement of the circuit, the final design specification is 12-bit 25MS/s SAR ADC. The design platform uses the TSMC 0.18um 1P6M COMS process. When the power supply is 1.8V, the input frequency is 1.214599609MHz for pre-simulation, SNDR is 73.6465 dB, ENOB is 11.95 bits, power consumption It is 1.7mW. The quality factor FOM is 17.51f J/conversion-step. The chip layout area is 1.190mm×1.190mm, and the core circuit area is 0.56mm×0.32um. Due to the signal delay in the layout, the sampling frequency can only be simulated at 20MHz at the fastest. The input frequency is 0.9716796875MHz for post-simulation, SNDR= 49.4647dB, ENOB=7.92 bit.

並列關鍵字

successive approximation register ； low power consumption ； ADC ； segmented capacitor array

參考文獻

[1] G.-Y. Huang, C.-C. Liu, Y.-Z. Lin and S.-J. Chang, “A 10-bit 12-MS/s Successive Approximation ADC with 1.2-pF Input Capacitance,” IEEE Asian Solid-State Circuits Conference, pp. 157-160 Nov. 2009.

Google Scholar

[2] W.-L. Son, H.-A. Majid, and R. Musa, “High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC” World Academy of Science, Engineering and Technology International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, 2012.