一個單通道六位元每秒八億次取樣的兩段連續漸近式類比數位轉換器

A Single-Channel 6-bit 800MS/s Two-Step SAR ADC

蔡承學(Cheng-Hsueh Tsai)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.10825

摘要

以40奈米CMOS一般製程製作一個單通道六位元每秒八億次的兩段連續漸近式類比數位轉換器。使用源極隨耦器做為緩衝器，將六位元連續漸近式類比數位轉換器拆開成前後兩級，此設計可直接使用工作週期50%的時鐘信號，因而省去複雜的週期信號產生器。另外，準位平移技巧加快約30 %的轉換率；任意選擇權重之電容陣列可補償前後兩級比較器造成的電壓偏移誤差，因此可省去電壓偏移校正電路。
根據晶片量測結果，在800MS/s的轉換率下的DNL和INL分別為+0.50/-0.42 LSB 和+0.65/-0.51LSB。在輸入頻率為393.8MHz且在800MS/s的轉換率下時，SNDR和SFDR 分別為35.3dB和45.6dB。在1V的供應電壓和800MS/s的轉換率下的功率消耗為3.72mW，換算成FoM為98 fJ/c.s.。全部的晶片面積大小為0.36mm2，然而主動電路所占的面積只有0.009mm2。

關鍵字

連續漸近式類比數位轉換器

並列摘要

A single-channel 6-bit 800MS/s two-step SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is fabricated in 40nm CMOS general–process technology. Using source follower as inter-stage residue amplifier, this work divides 6-bit SAR ADC into two stages for directly using external 50% duty clock. In other words, no duty cycle generator, which generates non-50% duty clock signal, is needed in this architecture. Proposed level-shift technique is used to accelerate ADC conversion rate by approximate 30%. Arbitrary weight capacitor array replaces calibration circuit to compensate errors caused by offset between comparators in the two stages.
According to measurement results, this prototype ADC exhibits DNL of +0.50/-0.42LSB and INL of +0.65/-0.51LSB at 800 MS/s. SNDR and SFDR are 35.3dB and 45.6dB at 800MS/s with 393.8MHz input frequency. The power consumption is 3.72mW at 1V supply voltage and at 800MS/s conversion rate. As a result, the FoM (Power/2ENOB/FS) is 98fJ/conversion-step. The whole chip including pads occupies 0.36mm2 while active area is only 0.009mm2.

並列關鍵字

SAR ADC ； Two-Step

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