一個使用二進位重組加權電容陣列的十位元連續漸進式類比數位轉換器

A 10-bit Successive-Approximation Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array

陳志玟(Chih-Wen Chen)

指導教授 ： 朱大舜

國立清華大學/電機資訊學院/電機工程學系所/碩士(2021年)

摘要

隨著科技的進步，5G通訊提供了更快的資料傳輸速度，以及更低的延遲，它應用到各個層面，家居、交通、醫療、農業，帶來了更便利的生活。而當中的類比數位轉換器是不可缺少的，他是大自然與電腦中間的橋樑，類比數位轉換器(ADC)的技術也持續不斷的在進步，往更高的解析度和速度發展。
本論文提出一個十位元每秒取樣一億四千萬次的連續漸進式類比數位轉換器(SAR ADC)，採用二進位重組加權的電容陣列架構。使用台積電65奈米1P9M製程，在供應電壓為1.2 V，輸入訊號為69.453 MHz，接近尼奎斯特頻率之下，靜態模擬得到的數據DNL及INL的分別為 -1/0.996 LSB以及 -0.998/0.723 LSB。訊噪失真比（SNDR）為59.7 dB，有效位元數（ENOB）為9.625 bits， 平均消耗功率為4.117 mW，核心電路面積為0.0316平方公釐。

關鍵字

連續漸進式類比數位轉換器 ； 加權電容

並列摘要

With the development of technology, 5G communication systems provide high data transmission speeds and low latency. It is applied to home, communication, medical treatment, and agriculture, bringing a more convenient life. The ADC is an essential block in the system. It’s an important bridge between the nature world and the computer. The technologies of ADC keep improving, toward to higher resolutions and better speeds.
A 10-bit, 140-MS/s successive-approximation analog-to-digital converter (SAR ADC) using a binary-scaled recombination weighting capacitor array is implemented in a TSMC 65 nm 1P9M CMOS technology. The supply voltage is 1.2 V. The DNL and INL are -1/0.996 LSB and -0.998/0.723 LSB respectively. The SNDR is 59.7 dB and the effective number of bits (ENOB) is 9.625 bits with input frequency is 69.453 MHz, near the Nyquist frequency. The power consumption in this work is 4.117 mW . The active area is 0.0316 mm2.

並列關鍵字

SAR ADC ； Binary-Scaled

參考文獻

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