十位元連續漸進式類比數位轉換器

A 10-bit Successive Approximation ADC

鐘鴻儀(Hong-Yi Chung)

指導教授 ： 盧志文

國立暨南國際大學/科技學院/電機工程學系/碩士(2010年)

摘要

本論文提出一個全差動式連續漸進式類比數位轉換器，具備有二權重式電容陣列網路。本架構前端添加了拔靴帶式開關，加速了電容網路之充電，減少了電容所需之穩定時間，同時又可以使電路正確地操作在低電源供應驅動開關之情況下。使用非同步電路在內部產生所需要之時脈，而不需要由外部時脈產生器供應。電容陣列採用同心圓方式佈局以減少底切效應之影響，以達到正確之電容陣列比值。
依據模擬結果，整個連續漸進式類比數位轉換器可操作在之5Ms/s取樣速率下，在2.5MHz之數入信號頻率下，其訊號雜訊失真比為58.696dB，有效位元數為9.458位元，積分非線性誤差為1.9LSB，微分非線性誤差為1.85LSB，總消耗功率為5.3mW，整體電路佈局面積為(含PAD) 1080um * 880um。

關鍵字

全差動式 ； 電容陣列 ； 連續漸進式類比數位轉換器

並列摘要

Propose a fully differentially successive approximation ADC with a binary-weighted capacitor array networks. Add bootstrapped switches to accelerate charging to the capacitor networks in front of this architecture, and decrease the settling time of capacitor array. Also keep circuit operate correctly under low supply voltage driving switches. Use asynchronous control logic to generate the necessary clock signals internally, rather then provide clocks by external clock generator. Unit capacitors of the capacitor array are laid out in a common-centroid scheme to reduce the undercutting effect, for achieving the correct ratio of capacitor array.
According to the result of simulation , the proposed ADC is designed to operate at 5Ms/s.Signal-to-noise and distortion ratio is 58.696dB, under the frequency of input signal is 2.5Mhz, the effective number of bit is 9.458 bit. The integral nonlinearity (INL) is 1.9 LSB. The differential nonlinearity (DNL) is 1.85 LSB. The power consumption is 5.3mW. Layout area of this architecture is 1080um * 880um.

並列關鍵字

Fully Differentially ； Capacitor Array ； Successive Approximation ADC

參考文獻

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[4]Cheng-Che Tang, "Design of a Pipelined Analog-to-Digital Converter", Master Thesis, National Chi Nan University, August 2008.

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