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  • 學位論文

每秒一千萬次採樣、十二有效位元之自我修正連續漸進式類比數位轉換器

A 10 MS/s, 12-ENOB SAR ADC with Self-Calibration in 0.18μm CMOS process

指導教授 : 徐永珍

摘要


本論文旨在設計並量測一類比數位轉換器,架構為連續漸進式,規格為十二有效位元、每秒一千萬次採樣。連續漸進式架構多以電容組成內部數位類比轉換器,帶來的詬病便是過大的面積及功耗。為減輕此種問題,本論文採用單調向下的切換機制以減少電容的面積及其功耗,並以自我比較器修正來減輕其電壓準位在位元轉換過程中不斷下降所帶來的偏移問題。 晶片使用TSMC 0.18 μm 1P6M CMOS製程實現,總面積為0.8 mm2,不含PAD之核心晶片面積為0.28 mm2,供應電壓為1.8 V、採樣頻率為每秒一千萬次、輸入差動弦波頻率在接近5 MHz、1.8 V振幅下之佈局前模擬結果,其有效位元數達到11.66,平均功耗為0.524 mW,INL與DNL之靜態模擬結果分別為( 1.49 / -1.88 LSB) 與 ( 2.14 / -1.00 LSB),量測可得最高有效位元數為7.78,於輸入訊號頻率700 Hz、採樣頻率900 kHz測得。

並列摘要


This paper presents an analog-to-digital converter(ADC), which is based on successive approximationn register structure(SAR). The specifications of the ADC is 12-bit ENOB and 10MS/s. Most of the SAR ADC use capacitance to build the DAC inside, which leads to larger area and power comsumption. To reduce its effect, the designed ADC uses monotonic switch mechanism and self-calibration of comparators to reduce the changing offset issue induced by voltage level going down during bits conversion phase. The chip is implemented under the TSMC 0.18 μm 1P6M CMOS process. The total chip area, including IO pads, is 0.8mm2 and the core circuit occupies 0.28 mm2. The supply voltage is 1.8 V, sampling frequency is 10 MHz. The pre-layout-simulation for input signal of almost 5 MHz, 1.8 Vpp shows 11.66 ENOB, 0.524 mW power consumption, the static simulation shows INL and DNL of (1.49/-1.88 LSB) and (2.14/-1.00 LSB). The highest ENOB measured is 7.78, which is measured with input frequency of 700 Hz, sampling frequency of 900 kHz.

並列關鍵字

ADC SAR Self-Calibration

參考文獻


[1] Walt Kester, “Which ADC Architecture Is Right for Your Application? ”
Analog Dialogue 39 - 06, June 2005
[2] Jacob Baker, "CMOS Circuit Design, Layout, and simulation ", 2010
[3] F. Kuttner, "A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 176-177, 2002.
[4] Chun-Cheng Liu, Soon-Jyh Chang, Member , Guan-Ying Huang, Ying-Zu Lin,

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