一個單通道六位元一次兩位元轉換每秒十二億次取樣的連續漸近式類比數位轉換器

A Single-channel, 1.2GS/s, 6-bit, 2-bit/cycle SAR ADC

林昇緯(Sheng-Wei Lin)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00685

摘要

以40奈米CMOS製程實現的一個單通道非同步六位元每秒十二億次的連續漸近式類比數位轉換器被提出來。
此設計中，使用了一次兩位元轉換的技術。比較於先前一次兩位元轉換的連續漸近式類比數位轉換器，此架只用了三排電容陣列，以節省硬體及功耗。 這本作品，以單通道達到每秒十二億次的取樣頻率。為了降低比較器的偏移電壓，本設計使用了基板端電容的前景校正方式。
此晶片量測結果，使用了不同的電壓以測試類比數位轉換器最大的速度效能。此連續漸近式的類比數位轉換器在供應電壓為1伏時，可達到每秒十億次取樣，功耗為4.18毫瓦。操作在1.1伏時，可達每秒十二億次取樣功耗為6.24毫瓦。取樣頻率為每秒十億次時，最高的SNDR可達34.75dB。取樣頻率為每秒十二億次時，最高的SNDR可達34.66dB。全晶片的面積大小為0.39 mm2，而主動電路所占面積只有0.016 mm2。

關鍵字

類比數位轉換器 ； 連續漸進式 ； 高速 ； 低功率 ； 一次兩位元轉換

並列摘要

A single channel, asynchronous, 6-bit successive approximation ADC with 1.2GS/s, in 40nm CMOS technology is proposed.
In this design, the 2-bit/cycle technique is used. Compared with the previously 2-bit/cycle, this architecture uses just three capacitor arrays to reduce the hardware and power consumption. In this work, single-channel, 1.2GS/s is achieved. This design uses the body capacitance foreground calibration in order to reduce the comparator offset voltage.
The measurements are performed with different supplies, in order to test the chips’ maximum performance of conversion rate. The SAR ADC can reach 1GS/s with a 1V supply, consuming 4.08mW. And it reaches 1.2GS/s with a 1.1 supply voltage, consuming 6.2mW. At 1GS/s, the peak signal to noise and distortion ratio is 34.75dB. When the sampling rate is increased to 1.2GS/s, the peak signal to noise and distortion ratio is 34.66dB. The ADC occupies an active area of 0.016 mm2, and whole chip with pads occupies 0.39 mm2.

並列關鍵字

Analog to digital converter ； SAR ； high speed ； low power ； 2-bit/cycle

參考文獻

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