採用時間交錯式技術之六位元每秒二十億次取樣的類比至數位轉換器

A 6-bit 2-Gsample/s Analog-to-Digital Converter with Time Interleaved Technique

林巍然(Vei-Ran Lin)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2010年)

https://doi.org/10.6837/NCNU.2010.00294

摘要

本論文提出一個六位元十億次取樣的快閃式類比至數位轉換器。此快閃式類比至數位轉換器的電路有：追蹤保持電路、六十四個比較器組成的比較器陣列、一個四通道的唯讀記憶體的編碼器和時脈產生電路。模擬結果顯示，快閃式類比至數位轉換器在輸入頻率100MHz時ENOB可達到5.899 bits，其功率消耗為568.69mW。
以十億次取樣的快閃式類比至數位轉換器為基礎，一個六位元二十億次取樣的時間交錯式類比至數位轉換器被提出。模擬結果顯示，時間交錯式類比至數位轉換器在輸入頻率100MHz時ENOB可達到5.315 bits，其功率消耗為1.2202W。

關鍵字

快閃式類比至數位轉換器 ； 時間交錯式類比至數位轉換器 ； 唯讀記憶體編碼器

並列摘要

In this thesis, a 6-bit 1GS/s flash ADC is presented. The ADC is composed of a track-and-hold circuit, a comparator array with 64 comparators, a four-channel ROM-based encoder, and its clock generation circuit. Pre-layout simulation shows that SNDR of 37.287dB and ENOB of 5.899 bits are achieved under input frequency of 100MHz and sampling rate of 1GS/s. The total power consumption is about 568.69mW.
Based on the 1GS/s flash ADC, a 6-bit 2GS/s time interleaved ADC is also presented. Pre-layout simulation shows that SNDR of 33.759dB and ENOB of 5.315 bits are achieved under input frequency of 100MHz and sampling rate of 2GS/s. The total power consumption is about 1.2202W.

並列關鍵字

Flash ADC ； Time interleaved ADC ； ROM-based encoder

參考文獻

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