應用於生理訊號擷取系統之10-bit、1.28MS/s連續漸近式類比至數位轉換器

A 10-bit 1.28MS/s SAR ADC for Bio-Medical Signal Acquisition System

林冠廷(Kuan-Ting Lin)

指導教授 ： 鄭桂忠

國立清華大學/電機資訊學院/電機工程學系/碩士(2013年)

摘要

近年來，生醫電子的發展越來越受到重視，特別是可攜式生理即時監測系統的相關產業更是蓬勃發展。配合攜帶型裝置的需求，低功耗、小體積成了這些系統中電路必然的發展趨勢。針對生醫訊號擷取系統，本論文提出10位元、1.28MS/s的連續漸近式類比至數位轉換器(SAR ADC)。其以單向式三級參考位準切換式電容陣列作為電路中的數位至類比轉換器(DAC)，其電容切換能量消耗及單位電容使用數僅為傳統式切換DAC的9.5%及25%。所設計之SAR ADC以TSMC 90nm CMOS製程實現，晶片總面積為1mm2而核心電路面積為0.205 mm2。在0.7V、1.28MS/s的量測下，SAR ADC的DNL為5.312/-1 LSB、INL為6.559/-3.932 LSB；在動態效能方面，SFDR為56.51dB、SNDR為47.13dB，而ENOB為7.53位元。其功率消耗為9.44uW，所達到之價值指標(FOM)為39.9fJ/conversion-step。為了有更好的效能，本論文另提出一10位元的SAR ADC，並同樣以TSMC 90nm CMOS製程實現，其DAC改以交替式三級參考位準切換式電容陣列實現，在電容數量不變的情況下，其平均電容切換能量消耗為傳統式切換DAC的13.5%，同時搭配可調偏移式比較器，以改善因DAC的不對稱切換所引發的動態偏移效應。此SAR ADC的晶片總面積為1mm2、核心電路面積則為0.14025mm2。在0.5V、1.28MS/s下，SAR ADC的量測DNL為0.646/-0.929 LSB、INL為1.556/-1.467 LSB；SFDR、SNDR及ENOB也分別提升至60.21dB、50.78dB、8.14位元。而此SAR ADC的平均功率消耗為4uW，FOM則改善為11.078 fJ/conversion-step。

關鍵字

類比至數位轉換器 ； 連續漸近式類比至數位轉換器 ； 電容式數位至類比轉換器

並列摘要

In recent years, the industry of the portable electronic devices for bio-medical signals monitoring has been significantly growing. For the requirement of these portable devices, low power dissipation and high hardware efficiency are the main goals of the circuit design for the bio-medical electronics.
A 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. In this SAR ADC, the DAC is functioned by a tri-level monotonic switching capacitive architecture. Its average switching energy is 9.5% to that of conventional switching capacitive DAC (CDAC), while its capacitor amount is 25% to that of conventional switching CDAC. The SAR ADC was fabricated in TSMC 90nm CMOS technology. The whole chip area was 1mm2, while the core circuit area was 0.205mm2. At 0.7V and 1.28MS/s, the static experimental performance of this SAR ADC were DNL of 5.312/-1 LSB and INL of 6.559/-3.932 LSB; the dynamic experimental performance were SFDR of 56.51dB, SNDR of 47.13dB, and ENOB of 7.53 bit. The SAR ADC dissipated power of 9.44uW, and achieved FOM of 39.9fJ/conversion-step.
For better performance, another 10-bit SAR ADC is presented and also fabricated in TSMC 90nm CMOS technology. To lessen the dynamic offset effect induced by asymmetric switching process of monotonic switching CDAC, the improved SAR ADC was formed by an offset adjustable comparator and a proposed tri-level alternative switching CDAC. The average switching energy of this CDAC was 13.5% to that of conventional switching CDAC. The whole chip area was 1mm2, while the core circuit area was 0.14025mm2. At experiment conditions of 0.5V and 1.28MS/s, this SAR ADC had DNL of 0.646/-0.929 LSB, INL of 1.556/-1.467 LSB, and its SFDR, SNDR, and ENOB were enhanced to 60.21dB, 50.78dB, and 8.14 bit, respectively. The power dissipation of this SAR ADC was 4uW, and the resulting FOM was improved to 11.078 fJ/conversion-step.

並列關鍵字

Analog-to-Digital Converter (ADC) ； Successive Approximation Register Analog-to-Digital Converter (SAR ADC) ； Capacitive Digital-to-Analog Converter (CDAC)

參考文獻

[2] R. Martins, S. Selberherr, and F.A. Vaz, “A CMOS IC for portable EEG acquisition systems,” IEEE Trans. Instrum. Meas., vol. 47, no.5, pp. 1191-1196, Oct, 1998.

[3] H.-J. Yoo and C.V. Hoof, Bio-Medical CMOS ICs Integrated Circuits and Systems, Springer, 2011.

[4] K. A. Ng, P.K. Chan, “A CMOS analog front-end IC for portable EEG/ECG monitoring applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 11, pp. 2335-2347, Nov. 2005.

[5] H.Y. Yang, R. Sarpeshkar, “A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 11, pp. 2349-2356, Nov. 2006.

[6] Behzad Razavi, Principle of Data Conversion System Design, AT&T Bell Laboratories, 1995.