具前景式校正機制之10位元１GHz 電流引導式數位類比轉換器

摘要系所別：電機工程學系　系統組論文名稱：具前景式校正機制之10位元1GHz電流引導式數位類比轉換器指導教授：朱大舜博士研究生：104061598 魏立帆隨著通訊系統的進步，數位傳輸的資料量越來越大，也因此類比數位轉換器和數位類比轉換器扮演的腳色越來越重要。而為了符合現今通訊系統的需求，高速、高頻寬和高動態範圍的轉換器將會是未來的趨勢。本論文主旨主要是在實現一個高速且高頻寬的數位類比轉換器，為了達到高速運作的需求，本文採用電流引導式數位類比轉換器，其速度限制主要來自於輸出端的時間常數(time constant)，方便於高速操作。但其中電流源彼此間的不匹配誤差(Mismatch)，將會影響數位類比轉換器的靜態和動態效能，而為了抵抗Mismatch的影響，除了增加電晶體的大小，我選擇使用另一種方法，利用電流源校正機制，對轉換器上的電流源做校正。在數位類比轉換器運作前，先依靠前景式校正機制，去對每顆電流源做修正，修正後數位類比轉換器再正常運作，由此可以節省電流源的面積，在小面積下就可以達到高精準度的高速數位類比轉換器。在晶片實現上，本文實現一個10bit數位類比轉換器在65nm製成的環境，在電源電壓2.5V下達到差動輸出0.8V的數位類比轉換器。晶片電路主要可以分為兩架構；數位類比轉換器、三角積分器。數位類比轉換器為電路主體，由電流引導式數位類比轉換器所組成，而三角積分器則是採用一階離散式的三角積分器，主要是用來校正數位類比轉換器上的電流源，使原本未校正前，輸入頻率50M、採樣頻率1GHz的數位類比轉換器的SFDR可以由58db提升到79db。

關鍵字

數位類比轉換器；電流引導式；不匹配誤差；前景式校正；三角積分器

並列摘要

Abstract As the communication system advances, the data of the digital transmission is growing rapidly.Therefore, the data converter plays the important role in the recent years. Also, high speed, high bandwidth and dynamic range are the future trend. The topic of the thesis is implementing the digital to analog converter in the high speed and high bandwidth requirements. For high speed operation, the work employ the current steering data converter which the limit of the speed depends on the time constant, and is convenient in high speed application. However the mismatch between the current sources rigidly influence the static and dynamic performance for the data converter. Except for using bigger size of the device, we use the calibration for the current source instead. Before the operation for DAC, we can adjust the current for the current source one to one in the foreground calibration method which can save the area and also achieve the high accuracy. In the implementation of the chip, my work employ the 10bit D/A converter in 65nm. The power supply is 2.5V and the differential output’s Vpp is 0.8V. The chip can split in two parts: the D/A converter, the delta sigma ADC. The D/A converter is built by the current steering DAC, and the delta sigma ADC which is used to sample the difference between current source implements in the first order discrete time delta sigma modulator. After the calibration, SFDR can be improved from 58dB to 79dB in Fin=50M, Fs=1GS/s.

並列關鍵字

Data Converter ； Current Steering ； Mismatch ； Calibration Method ； Delta Sigma Modulator

參考文獻

[1] A. Van den Bosch et al., “A 12b 500MSample/s Current-Steering CMOS D/A Converter,”ISSCC Dig. Tech. Papers, pp. 366-367, 2001.

[2] Cong, Y., and Geiger, R.L., “Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 47, pp. 585–595, 2000

[3] L.R. Carley, “ A noise shaping Coder Topology for 15+ bit Converters”, IEEE journal of solid state circuits, April 1989.

[4] W.-T. Lin and T.-H. Kuo, “A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection,” IEEE JSSC, vol. 47, no. 2, pp. 444-453, Feb. 2012.

[5] Wei-Te Lin and Tai-Haur Kuo, "A 12b 1.6GS/s 40mW DAC in 40nm CMOS with > 70dB SFDR over entire Nyquist bandwidth" 2013, 474-475, 2013

國際替代計量

具前景式校正機制之10位元１GHz 電流引導式數位類比轉換器

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