操作於低供應電壓每秒10萬次取樣之逐漸逼近式類比數位轉換器

本論文提出一個應用於可攜式與穿戴式產品中之低供應電壓每秒10萬次取樣之逐漸逼近式類比數位轉換器，為了達到低功耗的目的，此晶片的工作電壓為0.6 V，且輸入為單端軌對軌的電壓訊號。晶片內所使用的數位至類比轉換器，採用二進位權重(Binary-Weighted)電容陣列，其單位電容使用多層三明治的結構，可以有效地降低整體電容值與功率消耗。本論文所提出的低供應電壓之逐漸逼近式類比數位轉換器晶片，使用國家晶片系統中心所提供的TSMC 0.18 μm 1P6M CMOS製程來設計與實現。從晶片後模擬結果顯示，在電源電壓為0.6 V，工作頻率為1.2 MHz，取樣率為100 kS/s，輸入頻率在1. 376kHz時，SNDR為61.379 dB，ENOB為9.904 bits，功率消耗為0.478 μW，FOM為4.16 fJ/conversion，INL為-0.687(LSB)至+0.625(LSB)，DNL為-0.499(LSB)至+0.500(LSB)。

關鍵字

逐漸逼近式類比至數位轉換器；低功耗；軌對軌輸入

並列摘要

A low-voltage 100Ks/s successive approximation ADC for the sensor in protable and wearable products is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.6 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multil-metal sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption. The low-voltage 100kS/s successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS process provided by Chip Implementation Center (CIC). From the post-simulation results at 0.6 V supply voltage, 1.2 MHz operating frequency, 100 kS/s sampling rate, and 1.376 kHz input frequency, an SNDR of 61.379 dB (ENOB of 9.904 bits) is achieved with 0.478 μW power consumption. The FOM is 4.16 fJ/conversion. the INL is -0.687(LSB) to +0.625(LSB), the DNL is -0.499(LSB) to +0.500(LSB)。

並列關鍵字

SAR ADC ； Low power ； Rail to rail input

參考文獻

[1] 李泰成, 類比CMOS積體電路設計(修訂版), 滄海出版社, 2005年.

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[2] Texas Instruments, sep. 2012, Using sensor controllers to reduce power consumption in mobile computing,embedded, available : http://www.embedded.com/design/power-optimization/4396126/Using-sensor-controllers-to-reduce-power-consumption-in-mobile-computing.