每秒十萬次取樣之十二位元低功率逐漸逼近式類比至數位轉換器

A Low Power 12-bit 100KSample/s Successive- Approximation Analog-to-Digital Converter

魏嘉良(Chia-Liang Wei)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2011年)

摘要

本論文中，實現一個每秒十萬次取樣之十二位元低功率逐漸逼近式類比至數位轉換器之設計。此轉換器晶片包含取樣與保持電路、數位類比轉換器、比較器和逐漸逼近暫存器。使用二進位逼近參考電壓來完成類比數位轉換器，使比較器部分，得以用簡單的架構來實現；在數位類比轉換器上，採用C-2C電容陣列與二進位權重電容混合的方式，來降低功率消耗。
本論文之晶片工作電壓操作在1V，工作頻率為1.4MHz，輸入頻率在13.281KHz時，SNDR為67.508dB，功率消耗為2.628μW，FOM為13.545 fJ/conversion。
此晶片使用國家晶片系統中心所提供的TSMC 0.18μm 1P6M CMOS製程來設計與實現，晶片之核心面積為0.171 × 0.219 mm2，整體晶片面積為0.68 × 0.78 mm2。

關鍵字

逐漸逼近式 ； 類比數位轉換器 ； 十二位元 ； 低功率

並列摘要

In this thesis, A low power 12-bit 100KSample/s successive-approximation(SAR) analog-to-digital converter(ADC) is presented. The ADC contains a sample and hold circuit(S/H), a digital-to-analog converter(DAC), a latched comparator, and a successive-approximation register(SAR). The ADC is constructed by using binary search to the reference voltage in order to using a simple comparator. The DAC employs the hybrid structure including a C-2C capacitors array and a binary-weighted capacitors array, which reduces the power consumption.
The 12-bit 100 KSample/s SAR ADC chip works at 1V, and 1.4MHz clock. When input frequency is 13.281kHz, the signal to noise distortion ratio(SNDR) is 67.508dB, the total power consumption is 2.628μW, and the average energy per conversion step is 13.545 fJ.
The chip is designed using TSMC 0.18μm 1P6M CMOS process provided by Chip Implementation Center(CIC). The core area of the chip is 0.171 × 0.219 mm2, and the total area including pads is 0.68 × 0.78 mm2.

並列關鍵字

SAR ； ADC ； 12-bit ； low power

參考文獻

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