一個應用在生醫訊號系統0.5伏特十位元每秒取樣一百二十八萬次的連續漸近式類比至數位轉換器

A 0.5-V 10-bit 1.28-MS/s Successive Approximation register ADC for Bio-Medical Signal Acquisition Systems

鄭有惟(Cheng, Yu Wei)

指導教授 ： 鄭桂忠

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

https://doi.org/10.6843/NTHU.2015.00644

摘要

近年來，應用在醫療檢測的電子電路設計越來越受到重視，特別是結合行動裝置或可攜式生理即時監測系統的相關應用更是發展得相當迅速。而符合攜帶型裝置的需求，低功耗、體積小成了這些系統中電路必然的發展趨勢。
配合前端生理訊號擷取系統，本論文提出0.5伏特、10位元、1.28MS/s的連續漸近式類比至數位轉換器(SAR ADC)。其中加入了電容切換判斷輔助電路，來針對不同的輸入電壓做判斷是否數位類比轉換器(DAC)中的大電容，需要參與電壓切換，藉此避免不必要的切換功率消耗，以及提升電路效能。所設計之SAR ADC以TSMC 90nm CMOS製程實現，晶片面積為868μm × 868μm而核心電路面積為260μm × 234μm。在0.5V、1.28MS/s的操作下，佈局後SAR ADC模擬的DNL為0.21/-0.3 LSB而INL為0.279/-0.1295 LSB；SFDR為76.42 dB、SNDR為61.549dB，換算之ENOB為9.93位元，電路總功耗為3W，其價值指標(FOM)為2.4fJ/conversion-step。在量測實驗下，電路的DNL與INL分別為0.58/-0.43 LSB及0.84/-0.63 LSB；SFDR為66.28dB、SNDR為56.66dB，而ENOB為9.12位元，功率消耗為3.86W，其FOM為5.59 fJ/conversion-step。
為了使SAR ADC效能更佳，本論文另提出一10位元的SAR ADC，並同樣以TSMC 90nm CMOS製程實現，主要將兩個額外作為輸入電壓判斷的比較器，以數位邏輯電路作為取代，藉此降低對類比電路對稱性以及寄生電容等不理想效應的考量。此SAR ADC的晶片總面積為868μm × 868μm、核心電路面積則為238μm × 200μm。在0.5V、1.28MS/s下，SAR ADC佈局後模擬的DNL及INL分別為0.20/-0.28 LSB、0.21/-0.16 LSB；SFDR為79.06dB、SNDR為61.67dB，ENOB則為9.95位元，電路功耗為2.92W，FOM為2.26fJ/conversion-step。而其量測DNL為0.56/-0.59 LSB、INL為0.57/-0.70 LSB；SFDR、SNDR及ENOB分別為66.97 dB、56.55 dB、9.1位元，電路功耗為3 W，而FOM則為4.38 fJ/conversion-step。

關鍵字

連續漸近式 ； 類比至數位轉換器 ； 生醫前端擷取系統

並列摘要

In recent years, the design on bio-medical electronics has been getting more emphasized, especially the relative application on mobile device or portable monitors for the on time bio-signal acquitsition system. Low power consumption and high hardware efficiency are the trend of the requirement of portable devices.
A 0.5-V 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. A capacitor switching detection circuit mainly constructed by two auxiliary comparators is applied to determine whether the high weighted capacitor in DAC should join the switching process or not for different input voltage cases. Through this detection, the wasted switching power can be avoided and also promote the performance of SAR ADC. The SAR ADC is fabricated in TSMC 90nm CMOS technology, and it is 868μm × 868μm of area for whole chip and 260μm × 234μm for the core circuit. At 0.5V and 1.28MS/s, the post-layout simulation results of SAR ADC are DNL of 0.21/-0.30 LSB, INL of 0.28/-0.13 LSB, SFDR of 76.42 dB, SNDR of 61.54dB, ENOB of 9.93 bit, power dissipation of 3μW, and FOM of 2.4fJ/conversion-step. For experiment, it achieves DNL of 0.58/-0.43 LSB and INL of 0.84/-0.63 LSB, SFDR of 66.28dB, SNDR of 56.66dB, ENOB of 9.12 bit, power consumption of 3.86μW, and FOM of 5.59 fJ/conversion-step.
In order to achieve better performance of SAR ADC, another 10-bit SAR ADC is presented and also fabricated in TSMC 90nm CMOS technology. The switching detect circuit is replaced by digital logic gates and lessen the analog circuit concerns such as matching and parastic capcaitors due to routing which induces from the two auxiliary comparators. The chip area are 868μm × 868μm for total and 238μm × 200μm for core circuit. At 0.5V and 1.28MS/s, its post-layout simulation DNL and INL results are DNL 0.20/-0.28 LSB、0.21/-0.16 LSB, respectively; SFDR of 79.06 dB, SNDR of 61.67 dB, ENOB of 9.95 bit, power dissipation of 3μW, and FOM of 2.36fJ/conversion-step. For experiment, it achieves DNL of 0.56/-0.59 LSB and INL of 0.57/-0.70 LSB, SFDR of 66.97dB, SNDR of 56.55 dB, ENOB of 9.1 bit, power consumption of 3 μW, and FOM of 4.38fJ/conversion-step.

參考文獻

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