一個低電壓十位元每秒取樣十萬次至五十萬次之逐漸趨近式類比數位轉換器

A Low Voltage 10-bit 100-kS/s to 500kS/s Successive Approximation Register (SAR) ADC

范敦庭(Duen-Ting Fan)

指導教授 ： 蔡宗亨

國立中正大學/工學院/電機工程學系/碩士(2016年)

摘要

本論文提出一個10位元其取樣頻率範圍為每秒十萬次至五十萬次非同步操作低功率的逐漸趨近式類比數位轉換器，供應電壓按適當的比例縮小，是為了達到在不同的取樣率中能最小化功率消耗的目的。另外，此架構採用4項技術，來增強電路中比較的時間及取樣的時間並且減少不必要的穩定時間，在整體的轉換上，使用混合低截止電壓(Low-Vth)元件使兩級式靴帶電路改善了92.25%的取樣速度，為了避免亞穩態的發生，此設計上提出一個亞穩態的偵測機制，此外；使用三組栓鎖的動態比較器與電容陣列共模準位提升技術來加快比較的時間，一個穩定時間的控制電路用來設計適當的穩定時間並符合10位元精準度的類比數位轉換器。在供應電壓為0.5伏且取樣頻率為每秒十萬次下，功率消耗為424奈瓦，得到的訊號雜訊失真比為56.35分貝，有效位元約為9.07位元。微分非線性誤差峰值、積分非線性誤差峰值分別為+0.6/-0.8 LSB 和+0.8/-1.3 LSB。每一次資料轉換所消耗的能量只有7.9毫微微焦耳。最後，此設計案在180奈米製程下實現，其核心電路只佔0.077毫米平方。
此外提出新型之三維電容與網狀式電容陣列，不僅增加了MOM電容的單位密度，也減少了走線連接的寄生電容，進而降低面積以及總電容值。經由量測驗證，在數位類比轉換器上此新架構電容可達到10位元的精準度。

關鍵字

逐漸趨近式類比數位轉換器 ； 低電壓 ； 低功耗 ； 亞穩態 ； 非同步

並列摘要

In this work, a 10-bit 100-to-500KS/s asynchronous low power SAR ADC is realized. The supply voltage is scaled down appropriately (0.5 to 0.65V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, there are four techniques adopted, enhancing the comparison time, sampling time and reducing unnecessary settling time on whole conversion. The Double-Boosted sample-and-hold (DBS) circuit utilizes low-Vth device, resulting improve 92.25% of the sapling speed. To avoid the Metastability happened at the low-voltage environment, we proposed Metastability Detection and use Triple-latch dynamic comparator (Tri-latch) with DAC common-mode Level Shift (DCMLS) to enhance comparison time, finally a settling time of timing control circuit is implemented for the suitable settling and accuracy requirements of the 10b ADC. At a 0.5-V supply voltage and a 100-KS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424nW, the effective number of bits (ENOB) is 9.07 bits, the peak DNL and INL are +0.6/-0.8 LSB and +0.8/-1.3 LSB, finally resulting in a figure of merit of 7.9 fJ/conversion-step. The ADC core occupies an active area of only 0.077 mm2 in 180nm CMOS.
Besides, we proposed the 3-dimensional unit capacitor structure. It’s not only increase density of capacitor MOM but also reduce routing on parasitic capacitance. Furthermore the structure decreases value of sampling capacitor and chip total area. Through the measurement verification, this architecture can meet accuracy of 10-bit DAC.

並列關鍵字

SAR ADC ； Low voltage ； Low power ； Metastability ； Asynchronous.

參考文獻

[35] 楊旭光, 鄭錦文, and 李秉鴻. "導波應用於長距離管線之非破壞檢測技術." 中興工程 102 (2009): 71-78.

[2] McCreary, James L., and Paul R. Gray. "All-MOS charge redistribution analog-to-digital conversion techniques. I." IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371-379, 1975

[3] Tai, Hung-Yen, Hung-Wei Chen, and Hsin-Shu Chen. "A 3.2 fj/c.-s. 0.35 v 10b 100ks/s sar adc in 90nm cmos." In 2012 Symposium on VLSI Circuits (VLSIC), pp. 92-93.

[7] Harpe, Pieter JA, et al. "A 26 W 8 bit 10 MS/s asynchronous SAR ADC for low energy radios." IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, 2011

[8] Ginsburg, Brian P., and Anantha P. Chandrakasan. "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC." Circuits and Systems (ISCAS), IEEE International Symposium on. IEEE, 2005 pp.184-187