A 12-bit Successive Approximation Register Analog-to-Digital Converter with Digital Calibration

使用數位校正電路之十二位元連續漸進式類比數位轉換器

陳彥丞(Yen-Cheng Chen)

指導教授 ： 張彌彰

國立清華大學/電機資訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00133

摘要

本論文提出應用於生理訊號的一個十二位元每秒五十萬次取樣頻率的連續漸進式類比數位轉換器。此轉換器利用0.13um製程來設計且操作電壓為1.2伏特。此連續漸進式類比數位轉換器包含取樣保持電路、比較電路、數位類比轉換器以及控制電路開關。設計上，取樣保持電路採用拔靴開關讓電路的線性度提高並減少訊號失真。比較電路是由動態再生閂鎖組成，其正回授能讓比較電路的輸出值更精確。在數位類比轉換器中使用分離式電容陣列的方法來減少整體的電容值和平均功率消耗。最後是連續漸進控制邏輯電路，架構上使用一組位移暫存控制轉換程序與一排資料型正反器分別控制分離式電容陣列。
由於在轉換器中，製程不匹配以及佈局誤差將會導致轉換器的效能降低，進而使輸出數位訊號準確度下降。在此提出一個在轉換器內部做自我校正功能的修復機制電路，能夠讓轉換器的效能能夠有所改善。由於比較器和電容陣列是連續漸進式類比數位轉換器的核心，稍有誤差便會造成輸出訊號錯誤。於是分別對比較器、分裂電容以及電容陣列裡的電容逐一修正。其中比較器校正電路採用粗略與精準分段校正程序來減少面積與功率消耗。此校正電路可以有效的降低比較電路的偏移誤差，並且修正分裂電容和電容陣列裡電容不匹配的效應。經由校正電路，能讓轉換器輸出訊號更準確，將有利於輸出端之後的訊號處理。

關鍵字

連續漸進式類比數位轉換器 ； 類比數位轉換器 ； 分離式電容陣列 ； 校正

並列摘要

The thesis presents a 12-bit 500KS/s successive approximation register (SAR) analog-to-digital (A/D) converter for biomedical applications. The A/D converter is designed in a standard 0.13μm CMOS process and operates at supply voltage 1.2V. The SAR A/D converter includes the sample-and-hold (S/H) stage, the comparator, the digital-to-analog (D/A) converter and the SAR control logic. In this design, we use bootstrapped switch for S/H stage is to improve the circuit linearity and reduce the signal distortion. The comparator is composed of the dynamic latched regenerative circuit which gives the output of comparator better accuracy because of its positive feedback. Adopting the split capacitor array in D/A converter is to decrease the total capacitance and average power dissipation. Finally, the SAR control logic circuit uses a form of level shift control conversion process and a row of D filp-flops for controlling the split capacitor array.
The performance of converter can be reduced due to the process mismatch and layout deviation, and thus the accuracy of the digital output declines. So the thesis proposes a self-correction circuits which improves the performance of the converter. Since the comparator and capacitor array are important in SAR A/D converter, and the output signal will be wrong at the slightest error. So we calibrate the comparator, attenuation capacitor and capacitors in capacitor array individually. In the comparator correction circuit, we use coarse and fine correction two stage procedures to reduce the area and power consumption. The correction circuit can effectively reduce the offset of comparator, and correct the mismatch in the attenuation capacitor and capacitors in capacitor array. The output accuracy of the converter is improved significantly for medical applications.

並列關鍵字

successive approximation register analog-to-digital converter ； analog-to-Ddgital converter ； split capacitor array ； calibration

參考文獻

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