具有冗餘位元和非整數分離式電容陣列的十二位元連續漸進式類比數位轉換器

12-bit SAR ADC with redundancy using non-integer and split capacitive-array DAC

蘇炫峰(Syuan-Fong Su)

指導教授 ： 朱大舜

國立清華大學/電機資訊學院/電機工程學系所/碩士(2021年)

摘要

近幾年來物聯網發展非常的迅速，物聯網可處理資料、遠程地收集環境中各種的資料和利用網路取回這些寶貴的資料。為了感測環境中的資料，類比數位轉換器為此系統中不可或缺的電路。在現代5G連接互聯網的情況下，物聯網的應用通常需要無線裝置，而低功耗的特性為無線裝置中重要的考量。在低功耗的考量中，連續漸進式類比數位轉換器為最近較流行的選擇。

本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒一點二億次取樣的速度下，使用了帶冗餘位演算法達到速度上的優化，並且提出一個新穎的電容矩陣架構縮小其面積且降低電容的耗能。直接切換邏輯的應用不但提升了速度，也使電容有更多的穩定時間。此類比數位轉換器具有高速、低面積的特性，可以用於時序交錯式的類比數位轉換器，透過通道並聯的方式，達到速度上的提升。

本論文之十二位元連續漸進式類比數位轉換器使用台積電65奈米CMOS製程來設計，在1.2 V供電以及每秒取樣一點二億次操作下，本電路可達到軌對軌輸入訊號的振幅為2.2 V，模擬結果為訊號與雜訊諧波比可達到72.6 dB，相當於有效位元為11.765，DNL為+0.1/-0.1LSB，INL為+0.16/-0.22 LSB，平均消耗功率為7.313mW。

關鍵字

類比數位轉換器 ； 冗餘位元 ； 連續漸進式類比數位轉換器 ； 非整數分離式電容陣列

並列摘要

The Internet of Things (IoT) has developed rapidly in recent years. IoT is a method that processes the data, collects environmental data remotely, and retrieves the results over the internet. To sense environmental data in this situation, analog-to-digital converters (ADCs) is an indispensable circuit in the system. In the era of modern 5G access to the internet, IoT applications typically require wireless devices. Low power consumption is a key feature of wireless devices. For this key point, the successive approximation register (SAR) ADC has become a popular choice.

In the thesis, we have proposed a high-speed SAR ADC with the redundancy algorithm to speed up the conversion rate. A novel capacitor array is proposed to scale down the area and the power consumption. Direct-switched SAR Logic not only speed up the conversion rate but also make cap array more time to stable. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhanced by channel shunting.

The 12 bits SAR ADC was fabricated in the TSMC 65 nm CMOS process. At 1.2 V supply voltage and 120 Ms/s sampling rate, this design achieves the full rail-to-rail input swing is 2.2 V peak to peak and signal to noise and distortion ratio (SNDR) 72.6 dB, equivalent to the effective number of bits (ENOB) 11.765. The peak DNL values are -0.1 to +0.1 LSB and the peak INL values are -0.16 to +0.22 LSB. The average power consumption is 7.313 mW.

並列關鍵字

SAR ADC ； redundancy ； non-integer ； split capacitive-array DAC ； ADC

參考文獻

[1] B. Goll, et al., Comparators in Nanometer CMOS Technology, Berlin, Germany: Springer, 2015.

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[3] Tertulien Ndjountche, CMOS Analog Integrated Circuits High-speed and Power-efficient Design, New York, CRC Press, 2011.

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