針對於非均勻快取架構之效能與耗電評估

Performance and Power Evaluation for Non-Uniform Cache Architecture

林柏宏(Po-Hong Lin)

指導教授 ： 洪士灝

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.00087

摘要

隨著半導體製程的進步，在未來的處理器中將會整合大容量的快取。然而傳統快取架構的存取時間會隨著快取容量增加而提升，快取存取時間增加將會影響系統整體效能，效能的降低也會影響系統的耗電量。為了解決大容量快取存取時間過長的問題，最近幾年，出現了非均勻快取架構，其將快取分割成許多相同容量的bank，使用NoC (Network-on-chip)來存取各bank內部資料，其根據存取資料在非均勻快取架構的位置，提供了不同的存取時間，存取距離核心越近的資料其存取時間越短，然而存取距離核心越遠的資料其存取時間越長。雖然非均勻快取架構能夠提供較好的存取時間但是其複雜的架構以及不同的搜尋方法，可能會消耗過多的能量，因此在本文中，我們以軟體模擬的方式了評估非均勻快取架構的平台，分析其效能以及消耗的能量，最後與傳統快取架構比較，證實在執行SPEC測試程式時，非均勻快取架構具有高效能與低耗電量的特性。

關鍵字

均勻快取架構 ； 非均勻存取架構 ； 能量消耗 ； 評估效能 ； 晶片網路

並列摘要

The shrinking of process technologies enables large caches to be incorporated into future chips. In traditional cache architecture, the cache access time increases with the cache size and would effect performance and energy consumption. To reduce the average cache access time, non-uniform cache architecture (NUCA) was proposed. While NUCA reduce the average cache access time, its complex architecture and logical policies may increase energy consumption. In this paper, we built a NUCA simulation environment to show that NUCA can reduce average cache access time and save energy consumption for the benchmark programs in our simulated study.

並列關鍵字

NUCA ； UCA ； energy consumption ； performance evaluation ； network on chip

參考文獻

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