三維積體電路之閘級成本評估

三維積體電路技術需要矽導通孔 (through-silicon vias, TSVs) 來幫助傳輸不同晶片層之間的信號。矽導通孔所佔用的晶片面積會導致三維積體電路的實體設計面臨嚴峻的挑戰。為了準確地評估三維積體電路的製造成本，本篇論文提出一個更精準的成本模型，且比起其他現有的成本模型，此成本模型可以產生更合理且更精準的實驗結果。此外，現今已發表的二維平面電路分割文獻，只專注於減少分割線 (net-cut) 的數量，本論文提出一個多層次且考量矽導通孔的三維積體電路分割演算法，並且提出一個簡易的閘級成本評估流程來評估三維積體電路的閘級成本。此外，本論文也提供了一個三維積體電路的擺置與繞線流程，利用現有的二維擺置器和二維繞線器。流程分為四個階段：(1) 層與層的全域擺置、(2) 矽導通孔的插入和考量矽導通孔的合法化、(3) 層與層的細部擺置、(4) 層與層的繞線。由於標準元件所在的實體晶片層數已在電路分割的階段決定，因此現有的二維擺置器可直接用來擺置標準元件。此外，由於矽導通孔的實體位置也已在矽導通孔插入的階段決定，因此三維繞線可以利用傳統的二維繞線器來實現。實驗結果說明，相對於現今平面電路分割器和三維擺置器的文獻，我們的演算法可以達到最佳的閘級成本與最少的矽導通孔數量。

關鍵字

三維積體電路；矽導通孔；閘級成本評估；分割

並列摘要

Through-silicon vias (TSVs) are required for transmitting signals between different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon area occupied by TSVs causes critical challenges to physical design for 3D ICs. To accurately evaluate the cost of 3D ICs, this work presents an enhanced cost model, and experimental results justify that this model is more accurate and reasonable than other existing ones. Besides, unlike most published 2D partitioning works that only minimize the number of net-cuts during partitioning, this thesis proposes a multilevel TSV-aware partitioning algorithm for 3D ICs which considers the area overhead induced by TSVs, and this algorithm helps to evaluate the cost for manufacturing 3D ICs. Moreover, this thesis provides a place-and-route flow of 3D ICs by using a well-known 2D placer and a commercial 2D router. The place-and-route flow consists of four stages: (1) layer-by-layer global placement, (2) TSV insertion and TSV-aware legalization, (3) layer-by-layer detailed placement, and (4) layer-by-layer routing. Since the physical layers of cells are decided during partitioning, an existing 2D placer can be directly applied to place cells layer by layer. Moreover, since the physical positions of TSVs are determined during TSV insertion, 3D routing can be easily accomplished by using a traditional 2D router. Experimental results show that our algorithm can significantly reduce the cost and the TSV count, compared with other partitioning and 3D placement works.

並列關鍵字

3D ICs ； TSVs ； Gate-Level Cost Evaluation ； Partition

參考文獻

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[8] X. Y. Dong and Y. Xie, “System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs),” in Proceedings of Asia and South Paci c Design Automation Conference, pages 234–241, Yokohama, Japan, January 2009.

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三維積體電路之閘級成本評估

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