考量功率限制之三維積體電路分割演算法

Three Dimensional Integrated Circuits Partitioning with Power Consideration

吳偉傑(Wei-Chieh Wu)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2011年)

https://doi.org/10.6840/cycu201100533

摘要

在三維積體電路(3D ICs)設計中，電路分割一直是很重要的一個課題，在晶片設計之中，如何決定各個邏輯閘擺放分層的位置，影響著電路成本、良率及散熱問題，因此如何找到一個分割結果，能使得晶片在power density限制之下，最小化矽穿孔(Through Silicon Via, TSV)及Total area overhead為一個很重要的課題，本篇論文提出一個考量功率限制之三維積體電路分割的方法。
在本篇論文中，我們先對電路平均功率做分析，依照邏輯閘啟動的頻率、電功率、電容，算出每個邏輯閘平均的電功率，將各層的邏輯閘平均電功率除上各層的總面積，即可算出各層的電功率密度。

本論文以multilevel的架構來對netlist進行連續地coarsening，使用FM-Like的演算法，分出一個符合power density限制的partition初始結果，再以這個初始partition結果，使用uncoarsening、2-way FM及k-way FM演算法最佳化其解。

本篇論文使用9個工業用的測試電路，實驗結果顯示出，我們與TSV driven做比較，signal TSV個數會些微的上昇，但是卻可以使用較少的power TSV，整體總TSV使用數目平均改進6%，本論文與2011年IC/CAD競賽隊伍做比較，其結果可以顯示出本程式有相當不錯的結果。此外我們將TSV driven partition與先前的論文做比較，程式執行時間是研究[17]的49.83倍快，是研究[18]的9.50倍快。

關鍵字

三維積體電路分割 ； 矽穿孔 ； 功率

並列摘要

In 3D IC Design, partition is always an important step problem in physical design. The partition results of netlist will affect circuit cost, yield and thermal dissipation. Therefore, to find a partition result that can minimize Through Silicon Via (TSV) and total area overhead under power density constraint becomes an import issue. In this paper we propose a three dimensional integrated circuits partitioning with power consideration algorithm.

First of all, we analyze the power of a circuit. We can calculate the average power by active frequency, power and capacitance of logic gate. Power density of each layer equals total cell power divided by the total area of each layer. The algorithm is based on a multilevel framework to coarsen the netlist successively to reduce the problem size. We used FM-like algorithm to get an initial partition result that satisfies power density constraint. Based on this initial partition result, we use uncoarsening, 2-way FM and k-way FM algorithm to refine our partition result.

In this paper, we used 9 industrial integrated circuits. The experimental results show that compared to TSV driven, the number of signal TSV increases slightly, but we use less power TSV. In average, this program reduces 6% in the total number of TSVs. Comparing to IC/CAD 2011 contest, the results show that this paper has very good results. Comparing to previous research works, the runtime of TSV driven partition algorithm is 49.83 times faster than [17] and 9.50 times faster than [18].

並列關鍵字

Three dimensional integrated circuit partition ； power ； Trough Silicon Via (TSV)

參考文獻

[19]. 鍾易霖, ”應用於三維積體電路之多階層電路分割演算法, 中原大學資訊工程研究所碩士論文, 2009.

[20]. 胡宇成, ”應用於三維積體電路之熱導向多階層電路分割演算法, 中原大學資訊工程研究所碩士論文, 2010.

[1]. D. Kung, R. Puri, "CAD Challenges for 3D ICs," in Proc. Asia and South Pacific Design Automation Conference, 2009.

[2]. E. Acar, IBM Research, 3D IC Workshop, National Tsing Hua University, Hsinchu, Taiwan, 2008.

[5]. K. Puttaswamy, G. H Loh, "Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors," in Proc. ACM/IEEE Design Automation Conf., pp. 622-625, June 2007.