應用於三維積體電路之多階層電路分割演算法

A Multilevel K-layer Partitioning Algorithm For Three Dimensional Integrated Circuits

鍾易霖(Yi-Lin Chung)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2009年)

https://doi.org/10.6840/cycu200900791

摘要

在本論文中，我們提出了一個多階層的電路分割演算法應用於三維積體電路的架構中。演算法是以multilevel的架構來對netlist進行連續地coarsen。在un-coarsening的過程中執行K階層電路分割的程序。目的為最小化矽穿孔(Through Silicon Via, TSV)的總數目同時也遵守各層面積的限制。各層面積為電路面積的總和加上矽穿孔(Through Silicon Via, TSV)所使用面積的總和再除以層數。將電路分割演算法應用於三維積體電路的架構。我們使用一個類似FM的資料結構並且應用critical net的分佈，因此在一個cell搬動完後對gain值的更新非常有效率。實驗數據顯示我們提出的演算法對於工業用的測試電路可以有效率地最小化TSV所使用的數目及得到比較小的area overhead。

關鍵字

K層分割 ； 三維積體電路分割 ； 矽穿孔

並列摘要

In this paper, we propose a multilevel K-layer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A K-layer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Vias (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area then divided by the number of layer. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify some critical net distributions such that after a cell move, the program may update gains very effectively. The experiments show that with the proposed algorithm can effectively produce good results with minimization the number of TSV and small total area overhead for the tested industrial cases.

並列關鍵字

Through ； hree dimensional integrated circuits partition

參考文獻

[11] Provided by Industrail Technology Research Institute (ITRI), Hsinchu,

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