應用於三維積體電路之熱導向多階層電路分割演算法

A Thermal-driven Multilevel Multilayer Partitioning Algorithm for Three Dimensional Integrated Circuits

胡宇成(Yu-Cheng Hu)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2010年)

https://doi.org/10.6840/cycu201000393

摘要

在本論文中，我們提出了一個熱導向多階層的電路分割演算法應用於三維積體電路的架構中。演算法是以multilevel的架構來對netlist進行連續地coarsen。在un-coarsening的過程中執行K階層電路分割的程序。目的為最小化矽穿孔(Through Silicon Via, TSV)的總數目及使晶片最高溫度下降並使各層溫度平均同時也遵守各層面積的限制。將電路分割演算法應用於三維積體電路的架構。我們使用一個類似FM的資料結構並且應用critical net的分佈，因此在一個cell搬動後對gain值的更新非常有效率。各層的溫度為thermal resistance乘上此層的平均power，平均power為各層元件的power乘元件的area的總和再除以此層面積。各層面積為電路面積的總和加上矽穿孔(Through Silicon Via, TSV)所使用面積的總和。實驗數據顯示我們提出的演算法對於工業用的測試電路與GSRC測試電路可以有效率地最小化TSV所使用的數目及得到比較小的area overhead。不考慮溫度的狀況下與2009 IC/CAD競賽[32]前三名結果相比，TSV平均改進55%、晶片面積平均改進6%。並使用GSRC電路與相關研究[30]相比，TSV數目平均改進54%。加入熱的考量後，使用工業用的測試電路測試不同的熱分佈，與尚未加入熱考量的結果比較，TSV增加但晶片最高溫度下降，各層溫度差變小。使用GSRC電路實驗結果與尚未考慮熱的結果比較，其溫度平均下降10%、TSV上升17%。考慮熱之GSRC電路實驗結果與研究[30]相比，TSV數目平均改進33%。

關鍵字

三維積體電路分割 ； 熱導向電路分割 ； 矽穿孔 ； K層分割

並列摘要

In this paper, we propose a thermal-driven multilevel K-layer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A K-layer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Vias (TSV), decrease the maximum temperature in chip, and decrease the temperature coefficient of variation while observing the area constraint for each layer. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify eight critical net distributions such that after a cell move, the program may update gains very effectively. The temperature in each layer is the thermal resistance multiplied by the average power of this layer. The average power is the summation of the power of each cell multiplied by the area of the same one then divided by the area of this layer. The area of each layer is the summation of circuit area and TSV area. The experiments show that the proposed algorithm can effectively produce good results with small number of TSV and small total area overhead for the tested industrial cases. Without temperature consideration, the average number of TSV improves 55% and the average chip area improves 6% comparing with the three winners in the IC/CAD 2009 contest [32]. And the result compared with reference [30] using the GSRC benchmark, the average number of TSV also improves 54%. After considering thermal effect, using the tested industrial cases the number of TSV is increased a little, the maximum temperature in chip and the coefficient of variation of temperature among layers are decreased comparing with the results without thermal consideration. Using the GSRC benchmark, the average maximum temperature decreases 10% and the average number of TSV increases 17% comparing the result without thermal consideration. And the average number of TSV improves 33% compared with reference [30].

並列關鍵字

Three dimensional integrated circuits partition ； K-layer Partition ； Thermal-driven partition ； Through Silicon Via (TSV)

參考文獻

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