在跨指令集架構動態二進制碼轉譯中利用非對稱單指令多資料流暫存器組態

近幾十年來單指令多資料流 (SIMD) 在執行效能與能源效率方面的優勢已經促使硬體廠商廣泛地將其應用在處理器上。此外，SIMD 暫存器組態——暫存器的數量與寬度，也隨著新指令集擴充的引入而在不同處理器架構上快速地演進與分歧。然而在透過動態二進制碼轉譯移植已經對客戶指令集架構最佳化的現存或商業應用程式至另一擁有較少但較寬 SIMD 暫存器的宿主指令集架構時，客戶和宿主指令集架構之間非對稱的 SIMD 暫存器組態目前尚未被妥善利用。而未充份使用宿主的 SIMD 平行度和暫存器容量會嚴重限縮執行效能而無法達到宿主的理論最大值。在這篇論文中我們提出一個稱為「暫存器溢出感知超字層級平行」 (Spill-aware Superword Level Parallelism, saSLP)的新動態二進制碼轉譯技術，將已對客戶指令集架構最佳化的二進制碼迴圈進行轉換，藉此完全利用宿主 SIMD 的平行度和暫存器容量。我們提出的 saSLP 演算法可將數個客戶較短的 SIMD 指令與暫存器合併為單一較長的宿主版本，藉此完全利用宿主 SIMD 的平行度並同時減少暫存器溢出。在真實硬體上的實驗結果顯示提出的演算法可分別在多個實際應用與標準測試程式的 ARMv8 NEON 至 x86 AVX2 以及 AVX-512 動態二進制碼轉譯中獲得 1.6 與 2.3 倍的執行效能增益，同時顯著地減少 97% 與 99% 的暫存器溢出。

關鍵字

跨指令集動態二進制碼轉譯；單指令多資料流向量化；暫存器溢出；超字層級平行

並列摘要

Processor manufacturers have embraced single instruction multiple data (SIMD) for decades because of its superior performance and power efficiency. The configurations of SIMD registers (i.e., the number and width) have evolved and diverged rapidly through various ISA extensions on different architectures. However, migrating legacy or proprietary applications optimized for one guest ISA to another host ISA that has fewer but longer SIMD registers through binary translation raises the issues of asymmetric SIMD register configurations. To date, these issues have been overlooked. As a result, only a small fraction of the potential performance gain is realized due to underutilization of the host's SIMD parallelism and register capacity. In this paper, we present a novel dynamic binary translation technique called spill-aware SLP (saSLP), which transforms binary loops optimized for a guest ISA to exploit longer host registers in terms of both data parallelism and register capacity. Proposed saSLP combines short guest SIMD instructions and registers to fully utilize the host's parallelism as well as minimize register spilling. Experiment results show that saSLP improves the performance by 1.6X (2.3X) across a number of benchmarks, and reduces spilling by 97% (99%) for ARMv8 NEON to x86 AVX2 (AVX-512) translation.

並列關鍵字

Cross-ISA Dynamic Binary Translation ； SIMD Vectorization ； Register Spilling ； Superword Level Parallelism

參考文獻

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在跨指令集架構動態二進制碼轉譯中利用非對稱單指令多資料流暫存器組態

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