以FPGA實現非同步二維離散餘弦轉換

FPGA IMPLEMENTATION OF ASYNCHRONOUS TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM PROCESSOR

顏以誠(Ye-Chen Yen)

指導教授 ： 林登彬

大同大學/電機資訊學院/電機工程學系所/碩士(2006年)

摘要

本篇論文主要是提出一個適用於CCITT標準的非同步二維離散餘弦轉換處理器與反二維離散餘弦轉換處理器設計，在非同步設計上是用Sutherland Micropipeline 來構成交握式管線設計，而在二維離散餘弦轉換處理的實現上，是用行列分解的方式，把整個架構分成兩個一維離散餘弦轉換處理器與一個行列轉置記憶體，並用Distributed Arithmetic(DA)的方法實現陣列的相乘積，取代乘法器的使用，減少面積與成本。

關鍵字

非同步數位電路

並列摘要

This thesis proposes an asynchronous discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) processor core compliant with the CCITT recommendation H.261. We use the Sutherland Micropipeline structure to implement an asynchronous pipeline. It makes the data transmit forward by handshake protocol. And we adopt row-column decomposition to separate two-dimensional DCT /IDCT into two one-dimensional DCT/IDCT and a transpose memory. In order to reduce area and cost, we introduce the distributed arithmetic (DA) to take the place of multiplier.

並列關鍵字

asynchronous digital circuits

參考文獻

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