應用於非同步與同步電路設計之混合式系統單晶片的功率與時序最佳化方法

Power and Timing Optimization for Hybrid SoC Designs with Asynchronous/Synchronous Designs

何冠賢(Kuan-Hsien Ho)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2013年)

https://doi.org/10.6342/NTU.2013.00209

摘要

系統單晶片為一種積體電路設計，其整合數個功能模組至一個晶片，形成完整的系統以實現使用者的需求。近年來，有越來越多系統單晶片的設計裡混合地使用非同步與同步電路為基礎的功能模組；晶片設計者們將這兩種類型的功能模組放置於同一個晶片裡，期望非同步電路能有助於製造出高效能的晶片。另一方面，製程的進步使得晶片設計者們能在相同尺寸的晶片裡放置比以往更多的功能模組；然而，放置更多的功能模組所付出的代價則是增加了晶片功率的消耗，晶片設計者們被迫在功能性與功率消耗上取得一個適當的平衡點。如何降低功率消耗也因此成為系統單晶片設計裡的一大挑戰。
對於這樣的功率問題，一種直接的處理方法則是去降低各功能模組的功率消耗；考量到混合地使用非同步與同步電路的系統單晶片，此論文提出兩個功率最佳化的方法，一個用於降低非同步電路的功率消耗，另一個用於降低同步電路的功率消耗。對於非同步電路，基於樣板的設計方法是一種常見的作法，其原理是透過事先設計的電路樣板來處理電路元件之間的通訊，以實現非同步電路的設計自動化；由於電路元件之間的通訊行為是電路樣板所事先定義的，所以，電路樣板的設計會大幅地影響所設計出的非同步電路的功率消耗以及其效能的表現；因此，此論文研究電路樣板的設計，並提出一個新的電路樣板設計；透過這個新的電路樣板，對於非同步電路的管線化設計的電路，能夠有效地降低電路裡因為突波的產生而造成的功率消耗。而對於同步電路，元件尺寸最佳化及臨界電壓分配這兩項技術是產業界的低功率設計流程裡常見的技術，這兩項技術在積體電路完整的開發流程裡也被廣泛地用來降低功率消耗；基於這兩項技術，此篇論文提出了一個系統化的最佳化流程，這流程裡會同時採用此兩項技術來降低電路的漏電功率消耗；為了進一步加速這整個最佳化流程，此論文另外也提出一個在不失去最佳解的情況下來降低問題複雜度的方法，以及兩個有效的平行化方法。
雖然上述的方法能夠降低電路裡功率的消耗，現代的晶片設計裡普遍在後期設計階段裡會經歷多次的工程修改命令；如此，電路很容易違反最初的時序規範，有鑑於此，此論文進一步提出兩項工程修改命令的時序最佳化方法：第一項是源自於電路合成時的技術映射的方法，憑藉重構子電路來修復整體電路的時序；第二項是源自於時鐘樹設計時的時脈規劃的方法，利用製造時鐘樹上時脈的歪斜來修復整體電路的時序。對於上述所提出來的各種方法，此論文都已進行實驗分析以顯示這些方法的有效性。在最後的部分，基於這些研究成果，此論文列舉了一些未來可能的研究方向。

關鍵字

系統單晶片 ； 非同步電路設計 ； 元件尺寸最佳化 ； 臨界電壓分配 ； 工程修改命令

並列摘要

A system on a chip (SoC) is an integrated circuit (IC) that integrates multiple functional blocks in a chip for a specific application. For high-performance applications, more and more SoC designs combine functional blocks of asynchronous and synchronous circuits into the same chip, where asynchronous circuits are expected to achieve higher performance than their synchronous counterparts. On the other hand, the decreasing feature sizes enable IC designers to integrate more functional blocks into a chip than ever before. As the scale of integration grows, the increasing power density, however, forces the designers to make a trade-off between the functionality and power consumption of their chips. Reducing power consumption thus becomes a crucial concern for modern SoC designs.

This dissertation presents two strategies to minimize the power consumption of asynchronous and synchronous circuits. For asynchronous circuits, template-based design flow is widely used to automate the design of modern asynchronous circuits, where template structures strongly correlate to the power consumption and performance of the resulting circuits. Consequently, this dissertation proposes an asynchronous template that can effectively reduce glitch power consumption of asynchronous pipelines. For synchronous circuits, gate sizing and threshold voltage (Vth) assignments are two key techniques in industrial low-power design flow. Gate sizing and Vth assignments can be applied throughout the entire RTL-to-GDS flow for power and timing optimization of chip designs. This dissertation presents a systematic framework using gate sizing and Vth assignments for leakage power reduction. To be efficient, this dissertation also presents an optimality-preserving problem-size reduction technique and two parallelization methods for the proposed framework.

Although the above two strategies are effective to power reduction, modern IC designs often undergo multiple engineering change orders (ECOs) in late design stages to repair design or specification errors. The resulting designs may not be able to meet their timing requirements. Consequently, this dissertation further presents two metal-only ECO techniques for timing optimization using spare cells. One is derived from technology mapping to restructure timing critical sub-circuits iteratively, and the other is derived from clock scheduling to utilize clock skew for timing optimization. Experimental results show the effectiveness and efficiency of all the proposed approaches. Finally, this dissertation provides some directions for future research.

並列關鍵字

System on a Chip ； Asynchronous Design ； Gate Sizing ； Threshold Voltage Assignments ； Engineering Change Orders

參考文獻

[1] ABC: A System for Sequential Synthesis and Verification. http://www-cad.eecs.berkeley.edu/~alanmi/abc.

[3] ISPD 2012 Discrete Gate Sizing Contest. http://archive.sigda.org/ispd/contests/12/ISPD 2012 Contest Results.pdf.

[5] United Microelectronics Corporation (UMC). http://www.umc.com/.

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[7] J. Bainbridge. Asynchronous System-on-Chip Interconnect. Springer, 2002.