透過您的圖書館登入
IP:3.145.201.71
  • 學位論文

應用於軟體自我測試之彈性化混合型電路錯誤模擬器

A Flexible Hybrid Fault Simulator for Software-Based Self-Test

指導教授 : 黃俊郎

摘要


應用軟體自我測試(software-based self-test)的技術可彌補傳統結構性測試的不足,並且能在客戶使用階段提升硬體可靠性(reliability)。我們建立了一套彈性的電路錯誤模擬器,利用邏輯閘層次電路及暫存器轉移層次電路的關聯性,保留準確度及有效提升模擬速度,並且提供使用者自由彈性設置欲模擬的錯誤模式。 我們所提出的電路錯誤模擬器目的為在程式或應用執行的過程中,評估所產生出的測試程式或執行片段的硬體錯誤偵測能力,進而規劃容錯方法以提升系統的可靠度。所應用的主要錯誤模型為電路老化效應(aging effect)所造成的硬體缺陷, 我們將錯誤模擬因為老化效應所造成的路徑延遲錯誤(path delay fault)及轉態延遲錯誤(transition delay fault),以偵測老化效應的初期現象。

並列摘要


The use of software-based self-test technology can compensate for the shortages of conventional structural test and enhance the hardware in-field reliability. We have developed a flexible hybrid fault simulator which utilizes both logic gate level and register transfer level simulation to retain the accuracy and reduce the fault simulation time. Furthermore, we provide users the flexibility to set the fault model to be simulated. The proposed fault simulator aims to detect the possible hardware faults during the execution of test programs or applications. Evaluating the fault coverage of the generated test programs/applications can help develop fault tolerance techniques to improve the reliability of the system. The target fault model is the hardware fault caused by aging defects. We model the fault behavior as the path delay fault and transition delay fault models for aging fault simulation.

參考文獻


[1] P. Nigh et al., "Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment," International Test Conference, 1998, pp. 43-52.
[2] P. C. Maxwell, V. Johansen and I. Chiang, "The effectiveness of Iddq, Functional and Scan Tests: How many fault coverages do we need?," International Test Conference, 1992, pp. 168-177.
[5] J. Gatej, Lee Song, C. Pyron and R. Raina, "Evaluating ATE features in terms of test escape rates and other cost of test culprits," International Test Conference, 2002, pp. 1040-1049.
[6] M. E. J. Obien and H. Fujiwara, "F-scan: An approach to functional RTL scan for assignment decision diagrams," International Conference on ASIC, 2009, pp. 589-592.
[8] P. Patra, "On the cusp of a validation wall," Design & Test of Computers, vol. 24, no. 2, 2007, pp. 193-196.

延伸閱讀