使用多相位取樣技術之高速連續時間至數位轉換器設計與實作

Design and Implementation of High-speed Continuous Time-to-Digital Converter Using Multiphase Sampling Technique

宋之維(Chih-Wei Sung)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.00148

摘要

本篇論文研究之主要目的，在於時間至數位轉換器(Time-to-Digital Converter, TDC)，又可以稱為時距數位化電路(Time Digitizer)的研製，其主要的功能係量測單擊信號(Single-Shot)波形脈寬或是起始/停止(Start/Stop)信號之間的時距，前述的單擊信號亦可將其上升以及下降邊緣視為起始與停止信號處理，其他相關同一般類比至數位轉換器(Analog-to-Digital Converter, ADC)的定義。近年來由於延遲鎖定迴路(Delay Locked Loop, DLL)廣泛應用在解決與時間相關的問題上，諸如時脈產生器(Clock Generator)、時脈誤差(Clock Skew)等，兼備穩定度高以及設計容易的特性，提供多相位時脈進行取樣，因此延遲鎖定迴路亦適合應用在時間至數位轉換器電路。
本研究分為兩個部份，第一部份是針對連續時距數位化電路進行研究，文中提出一個兩級內插的架構，可以同時處理連續週期的信號而不必進行任何的重置(Reset)，並使用一個相對轉換概念取代傳統在後期加入額外的數位轉換電路，可在一個參考時脈週期的時間內完成轉換，達到高速轉換的特性。在電路的層面，同時提出一個新型的邊緣合成器應用在延遲鎖定迴路倍頻電路(Frequency Multiplier)，藉此產生後期電路的高頻參考時脈，故不需要額外的高頻輸入訊號，如此亦可達到一般可攜帶式(Portable)的應用。使用0.18-um CMOS 1P6M製程，在輸入操作頻率為200MHz下，最快輸入連續信號可達400MHz，解析度為78.125ps，僅需要16個延遲單元下達到兩級內插級數為64。晶片測量結果INL介於-0.99~0.98LSB，DNL介於-0.62~0.51LSB，整體晶片面積為1.1 mm x 1.0 mm。
第二部份主要著重於更高的解析度，採用相位內插器(Phase Interpolator)達到高解析度，在操作頻率為400MHz下，僅僅使用了12個延遲單元達到了總共128個內插級數，兼具了前述的所有優點，不失其連續取樣、相對時距轉換特性。使用0.18-um CMOS 1P6M製程來實現，解析度提高了400%至19ps，對於功率消耗的部份更是只需要不到50%的78mW，在線性度的表現上，INL介於-1.19~1.45LSB，DNL介於-0.69~0.79LSB，如此高解析度特性更是未來時距量測系統的主力。

關鍵字

時間至數位轉換器 ； 延遲鎖定迴路 ； 多相位產生器 ； 邊緣合成器 ； 連續轉換

並列摘要

The main purpose of this thesis lies in the design and implementation of a Time-to-Digital Converter (TDC) which is also named as Time Digitizer. It is used to measure the pulse width of a single-shot pulse or the time interval between Start and Stop signals. The former signal, a single-shot pulse, the rising and falling edges can also be treated as the Start and Stop signals, respectively. The main principle and some definitions are similar as an Analog-to-Digital Converter (ADC). In recent years, Delay Locked Loops (DLLs) are widely used in many timing applications, such as clock generator、clock skew, etc. Due to the considerations of design facility and stability, DLLs are generally employed in modern TDC design.
The thesis is divided into two parts. The first part of the research is to realize continuous conversion time digitizer circuitry. Two-level conversion scheme is proposed in this part. Continuous signals propagate and are digitized at the same time without any reset mechanism. The concept of relative timing conversion is in replace of additional digital circuits. The conversion time is within a period of the reference clock to achieve the characteristic of high-speed operation. Mentioned to the circuit field, a novel edge combiner is proposed to multiply the external reference clock to the higher one which is served as the clock of the latter stage circuitry. It does not require any extra input clock for most portable usage. The chip is fabricated in 0.18-um CMOS 1P6M technology. With an input reference clock of 200MHz and a continuous signal of the maximum frequency of 400MHz, the proposed TDC achieves 78.125ps resolution. It simply adopts 16 delay elements to attain the interpolation ratio of 64. From the measurement results, the INL is within -0.99 LSB to 0.98 LSB and DNL is within -0.62 LSB to 0.51LSB. The whole chip roughly occupies the area of 1.1mm2.
The second part of this thesis focuses on higher resolution. It uses a phase interpolator to reach higher resolution. With an input reference clock of 400MHz and a continuous signal of the maximum frequency of 300MHz, the second design adopts only 12 delay elements to achieve the interpolation ratio of 128. It covers all of the above advantages and maintains its features of continuous sampling and relative timing conversion. This design is realized in 0.18-um CMOS 1P6M technology. The resolution increases 400% to 19ps. As to power dissipation, it requires only 50% of the previous work to 78mW. In the performance of linearity, the INL is within -1.19 LSB to 1.45 LSB and DNL is within -0.69 LSB to 0.79LSB. Such a high resolution TDC will be the main character on timing measurement in the future.

並列關鍵字

Time-to-Digital Converter (TDC) ； Delay Locked Loop (DLL) ； edge combiner

參考文獻

[37]C.-C Hung, “Design of a CMOS Delay-Locked-Loop for clock generator applications”, M.S. Thesis, NTU, 2005.

[1]D. Santos, S. Dow, J. Flasck, and M. Levi, “A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip”, IEEE Trans. Nucl. Sci., vol. 43, pp. 1717–1719, June 1996.

[2]B.-K. Swann, B.-J. Blalock, L.-G. Clonts, D.-M. Binkley, J.-M. Rochelle, E. Breeding and K.-M. Baldwin, “A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications”, IEEE J. Solid-State Circuits, vol. 39, pp. 1839-1582, Nov. 2004.

[3]J.-P. Jansson, A. Mantyniemi and J. Kostamovaara, “A CMOS time-to-digital converter with better than 10 ps single-shot precision”, IEEE J. Solid-State Circuits, vol. 41, pp. 1286-1296, Mar. 2006.

[4]P.-M. Levine and G.-W. Roberts, “High-resolution flash time-to-digital conversion and calibration for system-on-chip testing”, IEE Proc.-Comp. and Dig. Tech., vol. 152, pp. 415-426, May 2005.