低電壓CMOS鎖相迴路於脈波產生器之設計研究

Research on the Design of Low Voltage CMOS Phase Locked Loops for Clock Generator

李宏斌(Hong-Bing Lee) ； 鐘文耀(Wen-Yaw Ghung)

《中原學報》 29卷3期 (2001/09) Pp. 293-301

https://doi.org/10.6358/JCYU.200109.0293

摘要

本論文主要在進行一應用於脈波產生器之低電壓CMOS鎖相迴路的設計研究。此電路主要是利用電荷充電泵之核心概念設計，其關鍵電路方塊由相頻偵測器、電荷充電泵、壓控振盪器、迴路濾波器，及除頻器所組成。
爲提高鎖相迴路抗雜訊及對溫度穩定之性能需求，本論文之相頻偵測器是採用可消除盲帶區雜訊影響的預充電架構來實現，而電荷充電泵所使用的定電流源爲可對溫度作補償的熱電壓參考電路，另外在數位雜訊的避免上也使用了非重疊電路作補償，壓控振盪器的部分使用了環振盪器，每一級皆使用差分輸入及差分輸出的放大器以避免抖動雜訊的發生。在迴路濾波器的部分，利用二階的系統以濾除相頻偵測器與電荷充電泵所產生的高頻雜訊，同時降低電壓跳動對壓控振盪器的影響。本研究採用並聯電容値之調整以求穩定度及足夠之相角限，除頻器兼具有除頻與輸出緩衝器之功能。本文所設計之鎖相迴路採用台灣積體電路製造公司0.35μm 1P4M製程來實現，佈局面積爲767.7μm^(上標 *)305μm，其規格爲2.7 V～3.3 V電源操作下，6 M Hz輸入訊號，可產生12M Hz、24M Hz、48M Hz與96M Hz四個訊號輸出選擇，其壓控振盪器最大頻率爲125M Hz，預估的抖動爲720ps，最大功率消耗爲10mW。本電路成果適合於系統晶片之頻率合成器與微處理器時序產生等應用。

關鍵字

低電壓CMOS鎖相迴路 ； 相頻偵測器 ； 電荷充電泵 ； 壓控振盪器 ； 迴路濾波器 ； 除頻器 ； 環振盪器

並列摘要

The aim of this thesis is to design a low voltage CMOS phase locked loop (PLL) for clock generator applications. The charge pump concept has been used in the PLL implementation and the core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter and divider.
This thesis adopts some methods below in order to improve the noise and stability performance of the PLL. Firstly, the frame of pre-charge stage is used to eliminate the noise of dead-zone in phase frequency detector. Secondly, the V(subscript T) reference circuit has been used to design constant current source in charge pump for temperature compensation, and the non-overlapping circuit is used to reduce the digital noise from the timing mismatch. The ring oscillator using fully differential input and output stage in voltage-controlled oscillator prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. The magnitude changing of parallel capacitor is used for obtaining enough phase margins. The divider provides both functions on frequency division and the output buffer for phase locked loop.
The chip has been implemented in the TSMC 0.35 μm 1P4M CMOS technology and the core layout area is 767.7 μm(superscript *) 305 μm. For 2.7 to 3.3V power supply, the input frequency is 6 MHz, and the output frequencies are12 MHz, 24 MHz, 48 MHz, and 96 MHz. The results show the jitter is 720ps at 6 MHz and the maximum power consumption is 10 mW at 3 V power supply. The proposed PLL has been shown its performance can be used in clock generator and frequency synthesizer applications.

並列關鍵字

Phase locked loop ； phase frequency detector ； charge pump ； loop filter ； divider and ring oscillator