應用於OC-12 SONET之622Mb/s時脈與資料回復電路

A 622Mb/s Clock and Data Recovery for OC-12 SONET Applications

周維駿(Wei-Chun Chou)

指導教授 ： 陳淳杰

中原大學/工學院/電子工程研究所/碩士(2006年)

https://doi.org/10.6840/cycu200600400

摘要

本論文主題在於設計一個應用在SONET OC-12 光纖網路通訊系統之622Mb/s時脈與資料回復器(Clock and Data Recovery Circuit)。此時脈與資料回復器主要是以鎖相迴路為基礎架構。其功能為從傳輸資料中回復所對應之時脈，並且利用此時脈重新對資料作取樣動作，達到資料與時脈同步效果。
本論文內容可分為五個章節，第一章為介紹時脈與資料回復器之應用背景，第二章則說明時脈與資料回復器所採取架構與適用於偵測隨機資料之各種相位偵測器。而第三章為探討系統設計考量，透過建立系統行為模型，與系統行為模擬，可以快速了解整體時脈與資料回復器之暫態特性，並且藉此可以迅速決定各項系統參數。而於第四章各區塊電路將被詳細探討，並且都以台灣積體電路製造公司(TSMC)之0.35μm 2P4M製程模擬完成。模擬結果顯示出時脈與資料回復器於供應電壓3V之下消耗功率為36mW，而均方根與峰對峰抖動值分別為12.4ps與59.7ps。最後，第五章為本論文之結論與未來展望。

關鍵字

電荷幫浦 ； 壓控振盪器 ； 相位偵測器 ； 時脈與資料回復器 ； 鎖相迴路

並列摘要

The goal of this thesis is to design a 622Mb/s Clock and Data Recovery (CDR) Circuit for SONET OC-12 optical networks. The CDR circuit is based on the structure of Phase Locked Loop (PLL).And, The function of the CDR circuit is to recover the clock information which is embedded into incoming data and resynchronize it with the incoming data.
This thesis could be divided into five chapters. Chapter 1 is introduction. The architecture of CDR and several phase detectors for random data is described in Chapter 2. Chapter 3 discusses the system consideration and the loop behavior model. From the behavior simulation, the CDR transient characteristic can be observed quickly. Thus, the parameters on the CDR can be evaluated as soon as possible. In Chapter 4, each blocks of the CDR circuit are discussed in detail. The Circuits were simulated with TSMC 0.35μm 2p4m CMOS process. Simulation results show that the CDR circuit consumes 36mW from a 3V supply voltage. The rms and peak-to-peak jitter of the output clock are 12.4ps and 59.7ps, respectively. Finally, the conclusion and future work are presented in Chapter 5.

並列關鍵字

Charge Pump ； Phase Detector ； Phase Locked Loop ； Clock and Data Recovery ； Voltage Controlled Oscillator

參考文獻

[16] Y. J. Chen, "Research on the Design of Low Voltage Charge-Pump Phase Locked Loops for Clock Generator," M.S.Thesis, Department of Electronic Engineering, Chung Yuan Christian University, 2003.

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