- 學位論文
應用於USB系統的全數位前饋型時脈與資料回復器
An All-Digital Feed-Forward CDR Circuit for USB
摘要
本論文先介紹傳統類比式與數位式的時脈與資料回復電路架構，再參考論文提出一個全數位前饋式時脈與資料回復器（All-Digital Feed-Forward CDR）並對相位偵測器電路修改，本電路包含Phase Detector、Digital Filter、Data Decision，所需時脈則由外部提供參考時脈。最後，本論文將前饋型CDR應用在USB系統上。 本系統架構均使用Verilog程式語言設計撰寫電路，並使用FPGA開發板Altera DE2-115實現，再用Tekronix DPO-7354示波器加以量測結果是否有符合USB系統的規格。 量測結果顯示：在1.5MHz(低速模式)和12MHz(全速模式)下的抖動量均小於規格書的規範，在480MHz(高速模式)下也有符合眼圖遮罩的規範，証明本論文的電路可以應用在USB的系統上。此外，模擬結果顯示當頻率偏移達0.5UI時會開始產生資料回復錯誤的情形，可推測Jitter tolerance為0.5UI，而回復資料時間為2 cycles。本論文的Total logic elements數目是884個。
並列摘要
This paper introduces the architecture of traditional analog CDR and digital CDR circuit first. Then, we propose an all-digital feed-forward CDR with modified phase detector. The proposed feed-forward CDR architecture is composed of phase detector, digital filter and data decision blocks with a reference clock. The proposed feed-forward CDR is applied to USB2.0 system to test its performance. In this paper, we use Verilog programming language to write the code of the architecture and implement it in Altera DE2-115 FPGA platform. The proposed CDR approach is measured by Tekronix DPO-7354 Oscilloscope and the results are compared with USB system specifications to observe their compliances. The measurement results show that in both the 1.5MHz (low speed mode) and 12MHz (full speed mode) operation modes, jitter is less than norm of USB specifications. In 480MHz (high speed mode), the performance is also meet the eye mask specification. The proposed CDR circuit in our paper can be used in USB2.0 system. In addition, the simulation results show that the jitter tolerance of the proposed CDR circuit is 0.5UI and the recovery time of the circuit is 2 cycles. Total logic elements of the circuit are 884 logics.