本論文提出一應用於Dual band groups MB-OFDM UWB系統之頻率合成器。此頻率合成器採用全新的Frequency-Planning,在電路架構上只需使用一個鎖相迴路搭配兩個單邊帶混波器即可,以達降低功率消耗及節省晶片面積之目標。 內容的部份可分為五個章節,第一章為介紹UWB超寬頻無線通訊系統以及研究目的,第二章則介紹頻率合成器的基本原理與架構,以及本論文之UWB頻率合成器基本架構與原理。而第三章為探討系統設計時的考量,透過Simulink建立系統行為模型,並進行模擬,可快速分析頻率合成器之暫態特性,藉以求得各項系統參數。而於第四章中將各電路架構做詳細的分析與模擬,最後第五章則為結論與未來展望。 本文所設計之頻率合成器採用台灣積體電路製造公司0.18um 1P6M RF CMOS製程來實現,不包含具ESD之PAD其佈局面積約為0.97mm*0.97mm,其規格為1.8V電源操作下,其頻段切換的時間約為0.8ns,最大電流消耗為67mA@1.8V,其Phase noise約為-110dBc@1MHz。共可輸出八個頻段,分別為3432、3960MHz、4488MHz、5016MHz、7656MHz、8184MHz、8712MHz及9240MHZ,滿足MB-OFDM UWB Band Group #1及#6等符合市場上使用的UWB頻段。
This proposal designs and realization of Frequency Synthesizer for Dual band groups MB-OFDM UWB Receiver. The frequency synthesizer is based on Frequency-Planning which is the lastest measure. Because of the power consumption and chip area, there are only one phase locked loops and two single-side band mixer in this frequency synthesizer. The proposal can be divided into five chapters. In the Chapter I, we introduce what is UWB, why the UWB so hot and what is the purpose in this proposal. In the Chapter II, we discuss the architecture of the proposed frequency synthesizer for dual band groups MB-OFDM UWB receiver. And introduce blocks function of the frequency synthesizer. In the Chapter III, we discuss the system consideration and the loop behavior model by using simulink. Simulink can save a lot of time in the transient analysis when we design the frequency synthesizer. In the Chapter IV, the transistor-level design of each building block is presented. The conclusion and future work are presented in Chapter V. The frequency synthesizer is designed in the TSMC 0.18 um 1P6M RF CMOS technology, and the active area is 0.97mm*0.97mm. The power consumption is 67mA from a 1.8 supply and the oscillator achieves a phase noise of -110 dBc/Hz at 1-MHz offset. The frequency synthesizer provides eight UWB frequencies in Band Group#1 (3432,3960MHz,4488MHz and 5016MHz) and Band Group#6 (7656MHz,8184MHz,8712MHz and 9240MHZ).