利用除小數頻率合成器製作之展頻時脈產生器

A Spread Spectrum Clock Generator Based on a Fractional-N Frequency Synthesizer

沈鼎璿(Ding-Shiuan Shen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10028

摘要

在可攜式裝置被廣泛使用之下，連接主要裝置與外部裝置的高速串列式連結變得越來越受歡迎，而對於減低一些不必要的電磁雜訊干擾(EMI)也是一個很重要的議題。在可攜式裝置中，主要的雜訊來源是在訊號處理單元與另一端像CD/DVD和HDD的周邊裝置之間的高速介面。SATA是其中一項最佳的技術，因為它能提供高達每秒3Gb甚至未來可達6Gb的大頻寬，而在SATA規格中，展頻時脈的技術可以透過分散主要載波的頻率來減低電磁雜訊干擾。
此外，除了在頻域上減低電磁雜訊干擾，考慮展頻時脈在時域上所造成的影響才是更重要的部分，因為在串列資料傳輸的過程中最主要關心的是訊號在時域上的完整性。為了達到這個目標，我們提出了一個低抖動展頻時脈產生器的架構，其中使用了一個8個相位的壓控震盪器(VCO)和雙模數小數除頻器(FDMP)。這個雙模數小數除頻器藉由小數的除數可得到一個比傳統雙模數除頻器好3/8倍的相位步階改進量。這個架構是利用0.18微米的CMOS製程來實現的，它可減低的電磁雜訊干擾量是14.77dB，而當展頻時脈功能開啟時，其均方根抖動量為5.55ps。我們也更進一步地利用90奈米的CMOS先進製程將這個架構進一步延伸去實現一個6GHz的展頻時脈產生器。這個架構透過加入了一個開迴路乘以2的電路去減緩在閉迴路時電路在時間和速度上所受到的限制，而模擬的電磁雜訊干擾減低量是25dB。
另外一個作品是製作了一個高速的40GHz除小數頻率合成器，它利用了一個我們所提出的可程式化多模數除頻器來實現。這個多模數除頻器能夠產生的最小除數步階量只有傳統架構的一半，因此，它能提供一個合理的頻率解析度和較佳的系統表現。這個架構是利用0.13微米的CMOS製程來實現的，而它所造成的小數凸刺量(fractional spur)可小於-50dB。

關鍵字

展頻時脈產生器 ； 低抖動 ； 預除器

並列摘要

As portable devices are widely used, high-speed serial links connecting hosts and external devices are becoming popular. Reduction of unnecessary radiation like EMI is a very important issue. Dominant noise sources in portable devices are high speed interfaces between signal processing units and the other peripheral storages, e.g., CD/DVD and HDD. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 3Gbps with possible extension to 6Gbps in the near future. In SATA, a spread-spectrum clocking (SSC) technique is specified to reduce the peak EMI emission by spreading the carrier frequency.
Besides EMI peak reduction amount in frequency-domain, it is more important to consider the time-domain impact of SSC since the major concern in serial data transmission is signal integrity in time domain. To achieve this goal, a low jitter 1.5 GHz spread spectrum clock generator (SSCG) is proposed which incorporates an 8-phase VCO and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to obtain a factor of 3/8 for phase step improvement compared with the conventional dual-modulus prescaler. This is implemented in a 0.18um CMOS process. The achieved EMI reduction amount is 14.77dB and the rms jitter is 5.55ps when SSC turned on. A further extension of this architecture is used to implement a 6GHz SSCG in a 90nm CMOS process. An open-loop multiply-by-2 circuit is incorporated into the architecture to ease timing and speed limitations in closed-loop operation. The simulated EMI reduction is 25dB.
Another work, a high speed 40GHz fractional-N frequency synthesizer, is also presented which incorporates a proposed programmable multi-modulus divider (MMD). The MMD is capable of providing a minimum divider step half of that in conventional MMD. Therefore, a reasonable frequency resolution and better system performance can be obtained. This is implemented in a 0.13um CMOS process and the resulted fractional spur is below -50dB.

並列關鍵字

spread spectrum clock generator ； low jitter ； prescaler

參考文獻

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