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  • 學位論文

展頻時脈產生器之設計與實作

Design and implementation of spread spectrum clock generator

指導教授 : 陳少傑
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摘要


在現今的積體電路設計中,系統單晶片(SoC)是一個主流方向。鎖相迴路及相關的電路更是必須朝向SoC方面發展。隨著製程進步,電晶體的尺寸越來越小但對於被動元件的尺寸來說沒有變小。低通濾波器是鎖相迴路其中的一個區塊,是由電容以及電阻所組成。在過去的幾年中,為了降低晶片面積跟成本通常將低通濾波器設計在晶片外部。為了達到SoC的目的,希望將迴路濾波器整合進入晶片當中。然而,這些迴路濾波器在晶片當中佔了相當大的面積。由於在展頻時脈產生器中,通常會有一個較小的頻寬。所以在較小的頻寬下會造成較大的低通濾波器。如果我們欲降低此迴路濾波器的面積,可以利用一個除二電路來達到此目的。

關鍵字

展頻時脈 鎖相迴路

並列摘要


Today System-on-Chip (SoC) is a mainstream for integrated-circuit design. PLLs are essential for SoC. The transistor size becomes much smaller when the CMOS process is improved, but not for on-chip passive components. A low-pass filter which is composed of capacitors and resistors is one of the building blocks in PLL. In the past years, a low-pass filter is always designed off-chip to reduce the chip size and production cost. Nowadays, a low-pass filter integrated into a chip is preferred for SoC. However, these passive components will occupy large area in a chip. We usually use a smaller bandwidth in a spread spectrum clock generator (SSCG), thus it will lead to a larger low-pass filter in the SSCG system. Since we want to reduce these passive components, a novel divided-by-two circuit is proposed and used in the PLL.

參考文獻


[1] “Spread Spectrum Timing for Hard Disk Drive Applications,” http://www.cypress.com, Nov. 2000.
[5] H. H. Chang, I. H. Hua and S. I. Liu, "A spread spectrum clock generator with triangular modulation," IEEE J. Solid-State Circuits, vol. 38, pp. 673-676, Apr. 2003.
[6] F.M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Communications, vol.28, no.11, pp.1849-1858, Nov. 1980.
[8] K. Hardin et al. “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, pp. 227-231, Aug. 1994.
[9] F. Lin and D.Y. Chen, “Reduction of Power Supply EMI Emission by Switching Frequency Modulation,” The VPEC Tenth Annual Power Electronics Seminar, Virginia Power Electronics Center, Blacksburg, Virginia, pp. 20-22, Sept. 1992.

被引用紀錄


Chang, C. Y. (2007). 應用於Serial-ATA之6GHz低相位抖動展頻時脈產生器之設計與實作 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2007.10449

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