時脈產生器、壓控震盪器及功率放大器之研製

Design of Clock Generator, Voltage-Controlled Oscillator, and Power Amplifier

謝易展(Yi-Jhan Hsieh)

指導教授 ： 江簡富

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.01137

摘要

在本篇論文中，我們利用標準TSMC 0.18 μm CMOS製程設計24 GHz的壓控振
盪器(VCO)、功率放大器(PA)以及6~100 MHz時脈產生器。
在VCO的設計方法中，我們透過使用NMOS與回授電容製作交錯連接負載
對，再製作三端變壓器回授來增加電感的品質因素及降低相位雜訊。此這個VCO晶
片的相位雜訊在頻率偏移1 MHz時，可達到-107 dBc/Hz，並透過NMOS變容器調整
輸出振盪頻率達到 1.23 GHz。在供應電源為 0.6 V 下所消耗的功率為2.6 mW，晶
片核心電流為 4 mA，晶片面積為0.39 mm × 0.56 mm。

在PA的設計中使用溫度補償電路做偏壓，溫度補償電路減少PAE與輸出功率隨
著溫度的衰減。本電路最高的小訊號增益為 20 dB，其最高輸出功率為20.6 dBm and
此時PAE為23.4%，3 dB頻寬為3.9 GHz，在供應電源為 0.6 V下所消耗的功率為 468
mW，晶片面積為0.52 mm × 0.34 mm。

在時脈產生器主要得設計挑戰為高時脈準確度與低抖動，使用低相位雜訊補償
型LC震盪器降低抖動。使用多數模除法器得到想要的輸出頻率，偏壓電路用來補償
溫度變異並使用線性穩壓器穩定壓控震盪器與除法器的電流其輸出頻率可以從6 至
100 MHz。

關鍵字

壓控震盪器 ； 功率放大器 ； 時脈產生器

並列摘要

In this thesis, A K-band voltage-controlled oscillator (VCO), a 24 GHz Power Amplifier
and clock generator have been designed and fabricated in a standard TSMC 0.18 µm 1P6M
CMOS technology.
A K-band voltage-controlled oscillator (VCO) with low phase noise is designed and im-
plemented in a 0.18 µm CMOS technology. By using an NMOS cross-coupled pair with
capacitive feedback, good circuit performance can be achieved in this band. A three-port
transformer is used to increase the quality factor and reduce the chip size. This VCO has a
low phase noise of −107 dBc/Hz at 1 MHz offset. Its tuning range is 23.22 to 24.45 GHz (5
%) at 0.6 V supply, and its core circuit consumes only 2.6 mW.
A 24 GHz power amplifier is integrated with a compensation circuit and implemented in
0.18 µm CMOS technology. The compensation circuit alleviates the change of power-added
efficiency (PAE) and output power due to ambient temperature and process variations. This
power amplifier is unconditionally stable, its power gain is 20 dB, the maximum single-ended
output power is 20.6 dBm, the PAE is 23.4 %, its 3 dB bandwidth is 3.86 GHz, and draws
130 mA of current from a 3.6 V supply. The chip size is 0.2552 mm2
.
A monolithic clock generator is designed and implemented using a 0.18µm CMOS process.
The main design goals include high clock-rate accuracy and low jitter. An 1 GHz harmonic
signal with low phase noise is generated using ring oscillator, which is then divided by
the multi-mode frequency divider to derive the clock signals. A bias circuit is designed to
compensate for the ambient temperature variation, and a low dropout regulator is used to
stablize the tail current. The clock rate can be tuned from 6 to 100 MHz.

並列關鍵字

VCO ； Power Amplifier ； Clock Generator

參考文獻

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