應用於有線及無線系統以數位時間轉換器實現之鎖相迴路及除頻器設計

Digital-to-Time Converter Based Phase-Locked Loop and Frequency Divider Design for Wireline and Wireless Applications

王敦儒(Tun-Ju Wang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800326

摘要

數位時間轉換器 (DTC) 被廣泛運用於各種時脈相關的應用，例如小數型鎖相迴路電路. 一個數位時間轉換器的延遲是由一個數位的控制碼來決定，延遲長度通常是從一組離散的元件中開啟特定的數量來控制，例如選取特定數量的延遲單位或是特定數量的充電電容。本論文將討論數位時間轉換器的應用。
本論文包含兩個作品，第一個作品為十五億赫茲以取樣鎖定鎖相迴路實現應用於展頻之時脈產生器，使用取樣鎖定(sub-sampling)之架構實現，並支援展頻調變。此作品的應用為有線系統中的時脈產生器，目標為降低對鄰近設備的電磁干擾量。本展頻時脈產生器實現於TSMC 180奈米製程。量測結果顯示本展頻時脈產生器在展頻調變開啟時，有18.98 dB之電磁干擾抑制。此外，輸出訊號量測得到之方均根時基誤差(RMS Jitter)為0.88 ps。此作品在1.8伏特下功率消耗為11.1毫瓦。
第二個作品為以相位切換實現之多輸出小數除頻器，使用相位切換之架構，支援多個不同頻率輸出，輸出頻率範圍為0.635-162.5 MHz。此作品的應用為供給單一系統晶片內，操作於不同頻率的各個子電路。以單一時脈產生器搭配數個本作品之除頻器，可節省多個不同頻率時脈產生器的面積以及功率消耗。本除頻器以TSMC 90奈米製程實現。量測結果顯示在不同的除數底下，本除頻器都能正確的運作。此作品並且可以同時支援不同除數，達到單一時脈輸入，雙時脈輸出的功能。

關鍵字

相位選擇器 ； 鎖相迴路 ； 展頻 ； 取樣鎖定 ； 除頻器

並列摘要

Digital-to-Time converters (DTC) have been widely used and it serves as one of the building blocks in many timing applications, such as the fractional-N PLL. The delay is of a DTC is controlled by a digital code, and the amount of delay is usually varied by switching on/off of a set of discrete elements, such as unit delay cells or charging capacitors. This thesis focuses on the applications of DTC.
This thesis includes two works. The first work is “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator”. This work employs a fractional-N sub-sampling PLL, and supports spread-spectrum clocking. This work aims to reduce the electromagnetic interference (EMI) of a clock generator with its neighboring devices. It is fabricated in TSMC 180-nm CMOS process. Measurement results have shown that the EMI reduction with spread-spectrum clocking enabled is 18.98 dB. Measured RMS jitter of the output signal is 0.88 ps. With a 1.8-V supply voltage, the power consumption is measured to be 11.1 mW.
The second work is “A 0.635~162.5 MHz Multiple Output Fractional Divider Using Phase Rotating Technique”. This work is realized by phase rotating technique, supporting multiple frequency outputs, with output frequency range of 0.635-162.5 MHz. This work aims to reduce the number of clock generators in a single SoC. It is fabricated in TSMC 90-nm CMOS process. Measurement results show that the proposed fractional divider functions properly under both integer and fractional division. Furthermore, this work supports dual outputs with two different division ratios, realizing a single input, multiple outputs frequency divider.

並列關鍵字

Phase Selector ； Spread-Spectrum ； Phase-Locked Loop ； Sub-Sampling ； Frequency Divider

參考文獻

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