具有自我迴路頻寬校正之全數位展頻時脈產生器與解展頻時脈產生器

All-Digital Spread Spectrum Clock Generator with Self-Calibrated Bandwidth and De-Spreading Clock Generator

古識涵(Shih-Han Ku)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10426

摘要

這篇論文主要著重於展頻與解展頻方法的研究。主題分別為具有自我迴路頻寬校正的展頻時脈產生器以及應用於DisplayPort的解展頻時脈產生器。兩顆晶片皆使用0.18um CMOS的製程，並以全數位的方式實現。不同於耗面積的類比濾波器，以高密度的先進製程實現的數位濾波效果可以達到較低的成本消耗。
　　第一顆晶片實現一個以PLL頻率暫態響應為基礎的展頻方法。提出的展頻架構利用切換除數以達到迴路頻率改變的效果，藉由選擇適當的阻尼係數，迴路頻率會呈現三角波形的變化，並達到所需的EMI下降量。晶片量測的結果，EMI下降14.37dB，RMS jitter在鎖頻及展頻模式下分別為1.49ps及1.49ps，峰對峰jitter則分別為13.33ps及19.90ps。
　　第二顆晶片實現一個解展頻的方法，將時脈從展頻訊號解出而不需額外石英振盪器。所提出的解展頻架構使用調變頻率校正電路及三角波相位延遲校正電路，調變頻率合成器的除數以抵消展頻調變，藉此達到解展頻的效果。

關鍵字

全數位鎖相迴路 ； 展頻時脈產生器 ； 除小數頻率合成器 ； 時間數位轉換器 ； 三角積分調變器

並列摘要

This thesis focuses on the research of a spread-spectrum method as well as a de-spreading method. Two topics of these chips are named as an all-digital spread-spectrum clock generator with self-calibrated bandwidth and an all-digital de-spreading clock generator for DisplayPort. They are both fabricated in a 0.18um CMOS process and implemented in an all-digital manner. In contrast to those area-consuming analog filter implementation, these proposed circuits implement the necessary filtering function in a digital way, which achieve a low-cost solution owing to the high density of modern CMOS processes.
　　The first chip is to realize the proposed spread-spectrum method without the accompanist of DSM quantization noise, which based on the frequency transient response of a PLL. In proposed SSCG, division ratio switching has been chosen as a manner to give the PLL loop a frequency step. By selecting a damping ratio properly, the transient frequency will have a triangular profile in time-domain and has an adequate EMI reduction. The measured EMI reduction of proposed SSCG is 14.37dB, where the RMS jitter is 1.49ps in locked mode and 1.49ps in spread mode. Also the peak-to-peak jitter is 13.33ps in locked mode and 19.90ps in spread mode.
　　The second chip is to implement the de-spreading technique, which regenerates a clock from a spread-spectrum clock reference without an extra crystal. The proposed crystal-less DSCG modulates the divided value of frequency synthesizer in order to cancel the spread-spectrum modulation, which is implemented by using a modulation frequency calibration and a triangular-wave phase delay calibration.

並列關鍵字

All-digital phase-locked loop (ADPLL) ； spread spectrum clock generator (SSCG) ； fractional-N frequency synthesizer ； time-to-digital converter (TDC) ； digital delta-sigma modulator (DSM)

參考文獻

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[2] S.-Y. Lin and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, pp. 3111–3119, Nov. 2009.

[4] H.-R. Lee, O. Kim, G. Ahn, and D.-K. Jeong, “A low-jitter 5000 ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18um CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2005, pp. 162–163.

[5] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΣΔ modulator with level shifter,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2005, pp. 160–161.

[6] K.-H. Cheng, C.-L. Hung, and C.-H. Chang, “A 0.77ps RMS jitter 6-GHz spread- spectrum clock generator using a compensated phase-rotating technique,” IEEE J. Solid-State Circuits, vol. 46, pp. 1198 - 1213, May 2011.