數位頻率校正機制與量化雜訊平移技巧之時脈資料回復電路設計

Design of Clock and Data Recovery Circuits with Digital Frequency Calibration Mechanism and Quantization-Noise Shifting Technique

劉丞恩(Cheng-En Liu)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.01245

摘要

時脈資料回復電路在有線通訊系統中扮演一個重要的角色，將經過長距離傳輸後具有雜訊和抖動的資料回復成乾淨的資料以利下一級電路的使用。在電路架構實踐上有許多選擇，如以鎖相迴路為基礎的系統、以注入式鎖定為基礎的系統、以相位內插器為基礎的系統等。本論文將分為兩個主要部份來介紹，第一部份將介紹一個採用注入式鎖定及數位頻率校正機制的10 Gb/s時脈資料回復電路，第二部份則將介紹一個使用相位雜訊平移技巧的25 Gb/s時脈資料回復電路。
在第一部份的10 Gb/s時脈資料回復電路中，先使用數位頻率追蹤機制將資料與時脈的頻率差縮小，注入式鎖定的技巧來追蹤資料的相位。量測的結果，在1.4伏特電源供應下消耗133 毫瓦，輸入資料速率為5 Gb/s和長度為27-1的PRBS得到時脈的峰對峰抖動和方均根抖動分別為77微微秒和12微微秒。
在本論文的第二部份的25 Gb/s時脈資料回復電路中，透過使用相位雜訊平移的技巧，在鎖相迴路中將多增至一組電流泵浦，此泵浦所產生的電流配合調變過後的控制訊號將可調整鎖相迴路的輸出相位，構成一個高相位精確度的相位內插器。量測的結果，在0.9伏特電源供應下消耗120毫瓦，相位雜訊在頻率偏差1 MHz為的地方為-96 dBc/Hz。

關鍵字

時脈資料回復電路 ； 頻率校正 ； 注入式鎖定 ； 量化雜訊 ； 相位內插器 ； 鎖相迴路

並列摘要

A clock and data recovery circuit plays an important role in wireline communication system. It removes the jitter and noise of received data caused by long-distance transmission. There are many choices for the implementation architectures, such as phase-locked loop (PLL) based, injection-locking based, and phase interpolator based systems. This thesis is divided into two parts. A 10 Gb/s CDR with injection-locking technique and digital frequency calibration and a 25 Gb/s CDR with quantization-noise shifting technique will be introduced.
A 10 Gb/s clock and data recovery circuit is implemented in the first part. A digital frequency-locked loop is used to track the frequency difference between input data and output clock. Then phase tracking is achieved by injection-locking technique. The measured power consumption is 133 mW under a 1.4 V supply voltage. The measured data peak-to-peak jitter and rms jitter under data rate 5 Gb/s and data length 27-1 PRBS are 77 ps and 12 ps, respectively.
In the second part, a 25 Gb/s CDR is implemented. Quantization-noise shifting technique is achieved by placing an additional charge pump in PLL. The modulated additional current adjusts the output clock phase of PLL to construct a high resolution phase interpolator. The measured power consumption is 120 mW under a 0.9 V supply voltage. The measured phase noise of free-running voltage-controlled oscillator is -96 dBc/Hz at 1-MHz frequency offset.

並列關鍵字

Clock and Data Recovery ； Frequency Calibration ； Injection-locking ； Quantization Noise ； Phase Interpolator ； Phase-Locked Loop

參考文獻

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