射頻金氧半場效電晶體高線性度混頻器和高輸出功率功率放大器之研究

Research of CMOS High Linearity Mixer and High Output Power RF Power Amplifier

陳飛飛(Feifei Chen)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201801325

摘要

此篇論文將介紹一個基於90 奈米互補式金屬場氧半導體製程的24 GHz 高線性度降頻混頻器和一個基於0.18 微米互補式金屬場氧半導體製程的4.6 GHz 高輸出功率功率放大器。第一個24 GHz的線性化混頻器，可應用於K頻段衛星通訊應用。第二個4.6 GHz的高輸出功率功率放大器，可應用於Wi-Fi系統。
首先使用90奈米金屬場氧半導體製程設計了24 GHz的高線性度降頻混頻器。為了在較低低功耗條件下達到較高的線性度，設計中採用了分佈式衍生疊加技術，折疊式架構，LC諧振技術。其中分佈式衍生疊加技術消耗的功耗較小，折疊式架構可以降低電源電壓，LC諧振技術能減少兩倍的LO諧波，該諧波會降低混頻器的線性度。由於採用了該技術，即使在線性器關閉的條件下，混頻器的IIP3也達到了16 dBm。當線性器打開時，IIP3為21 dBm。該混頻器的增益為-3 dB，功耗為10 mW。
而後使用0.18 微米製程，設計一個工作在4.6 GHz的基於變壓器結合的工作在class B的高輸出功率功率放大器。該設計中用變壓器並聯電容的方式代替傳統的電容電感共振電路，使得電路的佈局更加的緊密。變壓器由M4，M5，M6 三層金屬組成。該電路的小信號增益到達了11.6 dB，飽和輸出功率為27.8 dBm，最大功率附加效率為32%。
關鍵詞：線性化混頻器，金屬場氧半導體，功率放大器。

關鍵字

線性化混頻器 ； 金屬場氧半導體 ； 功率放大器

並列摘要

This thesis presents a 24-GHz down-conversion 90-nm CMOS high linearity mixer and a 4.6-GHz high output power 0.18-μm CMOS power amplifiers (PA). The mixer is designed with linearizer, which can be applied for satellite communication. And the PA is designed with high output power, which can be used for Wi-Fi communication system.
Firstly, a 24-GHz 90-nm CMOS high linearity down-conversion mixer is presented. The mixer utilizes distributed derivative superposition (DS) linearization technique, folded architecture, LC tank to achieve high linearity with relatively low power. The distributed DS linearization technique has little influence on dc power. The folded architecture reduces the power supply voltage. The LC tank reduces the 2fLO component which degrades linearity of the mixer, and thus, the mixer can achieve 16-dBm IIP3 with linearizer off. The IIP3 is 21 dBm with linearizer on. The mixer provides -3-dB conversion gain and the dc consumption is 10 mW.
Secondly, a 4.6-GHz transformer-based class B power amplifier with high output power implemented in 0.18-μm CMOS is designed. Instead of using inductors and capacitors, the transformer is used to attain a compact size. The transformers in this design are implemented using layer M4, M5 and M6 in 180-nm CMOS. This work achieves the small signal gain of 11.6 dB and output power of 27.8 dBm with power added efficiency (PAEmax) of 32%.

Index Terms —Linearized, CMOS, power amplifier.

並列關鍵字

Linearized ； CMOS ； power amplifier

參考文獻

[1] X. Guan, H. Hashemi, and A. Hajimiri, "A fully integrated 24-GHz eight-element phased-array receiver in silicon," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2311-2320, Dec. 2004.

[2] A. Natarajan, A. Komijani, and A. Hajimiri, "A fully integrated 24-GHz phased-array transmitter in CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2502-2514, Dec. 2005.

[3] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, "A 77-GHz phased-array transceiver with on-chip antennas in silicon: Transmitter and local LO-path phase shifting," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2807-2819, Dec. 2006.

[4] W. L. Chan and J. R. Long, "A 60-GHz band 2 X 2 phased-array transmitter in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2682-2695, Dec. 2010.

[5] A. Valdes-Garcia et al., "A fully integrated 16-element phased-array transmitter in SiGe BiCMOS for 60-GHz communications," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2757-2773, Dec. 2010.