高遷移率應變鍺通道場效電晶體

High Mobility Strained-Ge Channel Field Effect Transistor

王珮齡(Pei-Ling Wang)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10043

摘要

極薄(~4nm)厚度的鍺通道磊晶長在(100)方向的矽基上，具有很低的缺陷密度。又由於受到壓縮應力，可提升電洞的遷移率，因此可應用於高速電晶體。經由拉曼量測，鍺通道受到壓縮應力~1.25%。觀察穿透式電子顯微鏡(TEM)和電激發光(EL)，應變鍺通道場效電晶體沒有明顯的缺陷。
為了要正確模擬應變鍺通道場效電晶體，首先要探討應力對於矽覆蓋層（Si-cap）/磊晶鍺(epi-Ge)異質接面的能隙和能帶變化。經由理論計算算出來的參數值將在模擬採用。
為了要得到更好的元件性能，結構設計的最佳化是必要的。我們分別探討磊晶鍺和矽覆蓋層的厚度對於元件的影響。磊晶鍺若太薄，無法有效侷限電洞在磊晶鍺層裡，但是若太厚，會有很多錯位(dislocation)發生。另一方面，矽覆蓋層是希望越薄越好，但是太薄會使鍺的擴散現象惡化，以致於氧化層和半導體的界面均勻度很差。模擬結果和理論顯示1nm矽覆蓋層和4nm磊晶鍺是不錯的選擇，因此接下來的實驗和模擬都以這個厚度來探討。
傳統的離子佈值源極/汲極 P型應變鍺通道金氧半場效電晶體在飽和區的電流是一般矽金氧半場效電晶體的2倍。在電容電壓特性曲線的反轉層區，有明顯的shoulder現象，顯示元件在經過一連串製程後，仍有矽覆蓋層。
我們也探討傳統的離子佈值源極/汲極 N型應變鍺通道金氧半場效電晶體。由於矽覆蓋層夠薄，因此電子的波函數可以穿透到具有較高遷移率的應變鍺。結果顯示於相對於一般的矽金氧半場效電晶體，電流提升40% 。
蕭基能障金氧半場效電晶體是未來很熱門的應用。以鉑為源極和汲極材料，二氧化矽為絕緣層所製作和模擬的應變鍺通道P型金氧半場效電晶體，結果顯示相對於一般的矽蕭基金氧半場效電晶體，電洞遷移率提升3.2倍。應變鍺通道和蕭基能障金氧半場效電晶體成功的結合，在CMOS的應用上，具有無窮的潛力。

關鍵字

應變鍺

並列摘要

A novel structure with a 4-nm-thick Ge layer epitaxially grown on Si substrate (100) was simulated and characterized for applications to high-speed transistors. Raman spectra confirmed the compressive strain (~1.25%) in the Ge channel. The ultra thin Ge (~ 4 nm) channel on Si substrate has advantages of low defect density and hole mobility enhancement due to the compressive strain. No conspicuous defect observed in transmission electron microscope (TEM) and the strong electroluminescence (EL) from epi-Ge (ε-Ge) indicates the low defect density.
For numerical simulations of strained-Ge channel devices, strain effects on the band alignments and bandgaps of the Si-cap/ε-Ge heterostructure have been analyzed. The corresponding parameters calculated by theories are applied in the simulations.
Optimization of structure design regarding Ge layer thickness TGe and Si-cap layer thickness TSiCap have been carried out in order to achieve better performance. Thinner TGe can’t confine hole wavefunction effectively while thicker TGe leads to more dislocations. On the other hand, thinner TSiCap are preferred since it can increase gate-to-channel capacitance, but may worsen Ge diffusion as well as non-uniform oxide/semiconductor interface. Simulations and theoretical results reveal that 1-nm-thick TSiCap and 4-nm-thick TGe are appropriate and thus are targeted in this work.
The drive current improvements of the conventional implanted source/drain strained-Ge channel p-MOSFETs compared with that of bulk Si are found to be ~2x at saturation region. The holes confinement shoulder is observed on the capacitance-voltage characteristics at inversion region, indicating that a thin layer of Si-cap remains after the device process.
Conventional implanted source/drain strained-Ge channel n-MOSFETs are also investigated. The Si-cap is thin (~1nm) enough to enable the electron wave function to penetrate into high mobility buried Ge layer. It exhibits ~40% current enhancement as compared to the bulk Si device.
Schootky barrier MOSFETs(SBMOSFETs) is a promising application in the future. The Pt Schottky barrier strained-Ge channel p-MOSFETs with the conventional SiO2 as gate dielectrics reveal a ~3.2x mobility enhancement. The successful combination of strained-Ge channel and SBMOSFETs shows great potential in the CMOS technology.

並列關鍵字

strained-Ge

參考文獻

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