第五代雙倍資料率記憶體資料緩衝器之驗證平台研發與訓練模式分析

Design and Development of Verification Platform for DDR5 Data Buffer and Its Analysis of Training Modes

田鈺光(Yu-Kuang Tian)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202202114

摘要

在過去的幾年裡，處理器的週期時間減少的要比記憶體週期時間快的多，而這導致了我們對更高性能的記憶體的需求。同步動態隨機存取記憶體 (SDRAM)必須在頻寬以及容量方面有所進步。因此，第五代雙倍資料率同步動態隨機存取記憶體 (DDR5 SDRAM) 作為新世代的雙倍資料率記憶體而被提出。
為了克服容量及速率上的限制，DDR5 SDRAM 具備了許多新功能，而這也導致 DDR5 SDRAM 的晶片設計複雜度增加，並且同時使其晶片的驗證變成困難的任務。相較於使用 Verilog 來進行驗證，SystemVerilog 提供了約束化隨機測試與物件導向的概念讓人使用。因此，他被廣泛運用來開發驗證平台。
在這篇論文裡，我們為 DDR5 的資料緩衝器 (DB) 設計了一個基於斷言式驗證的可具有不同配置的驗證平台。我們開發了一個可以計算功能覆蓋率的模型，並且用不同的測試案例來提升功能覆蓋率。所有的 405 個斷言都在模擬中被 170個測試案例覆蓋到也證明了我們的平台的有效性。
我們分析了 DDR5 DB 驗證的其中一個關鍵環節，也就是資料緩衝器訓練模式。我們分析了他與 DDR4 DB 的訓練模式的不同，並且展示了他們的不同對於他們的驗證過程會有什麼影響。

關鍵字

第五代雙倍資料率記憶體 ； 資料緩衝器 ； 訓練模式 ； 驗證

並列摘要

Over the years, processor cycle time has decreased much faster than memory cycle time, giving rise to the need for high-performance memory systems. SDRAMs must improve their bandwidth and capacity. Therefore, The fifth-generation double-data-rate (DDR5) SDRAM has been proposed as the next-generation DDR SDRAM.
With the various new functions to overcome scale and speed limitations, the complexity of DDR5 SDRAM chip design is increasing, and verification is becoming a difficult task. Compared to Verilog verification, SystemVerilog provides constrained random verification and OOP concepts to work with. Therefore, it is widely used to develop a verification platform.
In this paper, we designed and implemented an assertion-based verification platform for DDR5 Data Buffer (DB). A bus functional model has been developed, and the coverage is collected based on the assertions covered by the test cases. With all the 405 assertions being covered by 170 test cases, the effectiveness of our work can be guaranteed.
We analyzed one of the critical parts of DDR5 DB verification, namely the DB training modes. We compare it with DDR4 DB training modes and show how their differences impact the verification process.

並列關鍵字

DDR5 SDRAM ； data buffer ； training mode ； verification

參考文獻

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