本論文分為兩個部分,一個是寬頻的分佈式放大器,另一個是250 GHz的基板壓控振盪器。本論文的第一部分描述了一個分佈式放大器的電路設計,採用台積電65奈米金氧半場效電晶體製程。此電路由兩個傳統的分佈式放大器及一個串接單級分佈式放大器所組成,並且從中利用這兩個架構的優點。除此之外,此電路使用了多驅動級間耦合技術,增加高頻的頻寬及高頻的增益。此電路使用了 0.68 mm2 的晶片面積,直流功率消耗為 254 mW。此分佈式放大器提供了30 dB的增益,3dB 頻帶寬為14至91 GHz。此電路可顯示2435 GHz的增益頻寬積,在已發表的CMOS分佈式放大器中,是最高的數字。本論文的第二部分是一個250 GHz基板壓控振盪器,採用了台積電65奈米金氧半場效電晶體製程。此壓控振盪器利用基板的電壓改變調整電晶體的寄生電容容值,進而調整振盪器的振盪頻率。該電路的輸出功率為 -10.4 dBm,直流功率消耗僅有16.9 mW,得出直流轉換功率為0.53%。此電路的可調頻率範圍為244.5 GHz至252.5 GHz,電路面積為0.09 mm2。與其他已發表之200 GHz以上射頻電路的振盪器相比,此電路擁有低功耗、面積小、及高直流轉換功率等性能。
This thesis is divided into two parts, one is a wideband distributed amplifier and the other one is a sub-terahertz voltage control oscillator. The first part of this thesis describes the design of a distributed amplifier using 65-nm CMOS technology. This circuit consists of two conventional distributed amplifier and one cascaded single-stage distributed amplifier, and takes the advantages of them. Also, the technique of multi-drive inter-stack coupling is used in this design for wider bandwidth and higher gain at high frequency. This proposed distributed amplifier occupies 0.68-mm2, and the power consumption of this circuit is 254-mW. The DA provides a 30-dB gain, and the 3-dB bandwidth of this DA is from 14 to 91 GHz. This circuit achieves 2435 GHz GBW product. To the authors’ knowledge, this circuit performs highest GBW product among the published CMOS DAs. Secondly, a 250 GHz VCO is realized in TSMC 65-nm CMOS technology. The VCO utilizes the body bias to control the parasitic capacitor of the transistors. This circuit has a -10.4 dBm output power with only 16.9-mW dc power dissipation, and the dc-to-RF conversion efficiency is 0.53%. The tuning range of the VCO is 244.5 to 252.5 GHz, and the chip size is 0.09 mm2. Compared with other published works, this VCO has low power consumption, small chip area, and high DC-to-RF efficiency at frequency higher than 200 GHz among MMW VCOs using CMOS process.