利用類神經網路於記憶體匯流排之訊號完整度分析

本篇論文提出以類神經網路架構，輔助分析記憶體匯流排中設計參數和其眼圖表現的非線性映射函數，並經由此函數找到最佳化設計。本論文利用這個方法在兩種不同的記憶體匯流排架構上做分析，第一種為工業界在第二代雙倍數據率同步動態隨機存取記憶體的位址/控制匯流排一對八的訊號傳輸設計，我們也嘗試利用類神經網路的輔助分析方式，用較高的自由度去設計此電路系統，但成效不高，最後我們使用電路面向去分析電路，用等效電路去探討最佳設計結果的原因。雖然如此，訓練完成的類神經網路能夠快速地對於同樣電路的不同需求，提出完整的設計方針。發現當此架構總長度不長時(<0.3λ)，只需要將特徵阻抗提高來補償電容效應即可。在第二種架構中，我們分析晶圓級封裝中，用於行動通訊硬體上的低功率雙倍數據率同步動態隨機存取記憶體第四代架構，運用類神經網路分析在下層重新分佈製程線路中的傳輸線尺寸設計，在不同的設計結構上，分析其表現並探討參數改變對於結果的影響，最後同樣以等效電路方式來印證分析結果。

關鍵字

類神經網路；訊號完整度；眼圖；晶圓級封裝；記憶體匯流排

並列摘要

In this thesis, we make use of Artificial Neural Network (ANN) approach to analyze the relation between design parameters and eye diagram performance of memory bus. Then we used the trained ANN function to find the optimal design for two kinds of memory structure. One is the one-to-eight CMD/ADDR/CNTR buses in flyby structure in DDR2 (Double-Data-Rate Two Synchronous Dynamic Random Access Memory).With ANN, we tried to design the structure in higher degree of freedom, but it didn’t help us to get much higher performance results. Therefore, we utilize the equivalent circuit to investigate the key point that effects the performance. Nevertheless, well-trained ANN can quickly suggest the design guideline for different demand in same structure. We find that when the total length of the flyby structure is not long (<0.3λ),it is easy to approach optimal design by letting the characteristic impedance higher. For another one we analyze the Low Power DDR4 (LPDDR4) transmission line design in the lower redistribution layer in InFO-WLP (Integrated Fan-Out Wafer-Level-Packaging) technology used for mobile devices with ANN. In different kinds of unit cell, we analyze the effect of design parameters on the performance and finally use the equivalent circuit to certify our result.

並列關鍵字

Artificial Neural Network ； Signal Integrity ； Eye diagram ； Wafter-Level Package ； Memory Bus

參考文獻

[22] 郭宗益(June ,2016 ). 改善晶圓級封裝電源完整度之雙層電源接地網格佈局優化法, 台灣大學碩士論文.

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利用類神經網路於記憶體匯流排之訊號完整度分析

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