- 學位論文
改善晶圓級封裝電源完整度之雙層電源接地網格佈局優化法
Optimized Two-layer Power-ground Mesh Layout for Power Integrity Improvement on Wafer-level Package
摘要
次世代晶圓級封裝技術的下層重新分配層是影響信號/電源完整度最大的結構，由於其走線又細又長、信號線眾多且佈線密度高的關係，有著極大的寄生電感、電容效應，使信號/電源的傳輸品質不佳，因此是整體封裝上最為棘手的設計。又因為封裝上的限制，無法任意擺放去耦合電容，僅能放置晶片內的去耦合電容，導致電源/接地間的寄生電感將會對下層重新分配層的電源完整度造成極度嚴重的影響。 本研究主要分為三大部分，一是提出了最佳雙層電源接地網格佈局設計來改善晶圓級封裝下層重新分配層，使其電源/接地間的寄生電感降低、寄生電容提升，進而獲得較佳的電源完整度；二是針對接收端信號上升曲線進行分析，提出接收端信號的增進方法為降低正規化電阻，透過此設計成功提升眼圖品質，並給予各佈局設計的橫截面積與最長走線距離的關係表，以利根據需求選擇設計佈局；三是信號換線佈局的設計，透過相鄰信號換線佈局模組，搭配鬼腳圖的數學理論分析，提出最短距離且最少層數的任意排列信號換線佈局設計演算法。 透過採納本研究所提出的最佳雙層電源接地網格佈局設計、接收端信號增進方法與任意排列信號換線佈局設計演算法，將有助於在次世代晶圓級封裝技術上的電路設計研發，給予設計指南並增加整體電路的性能。
並列摘要
The next generation wafer-level packaging technology suffers from serious signal and power integrity issues due to lower re-distribution layer (RDL). Because of serious parasitic effects caused by the high-density lower RDL traces, the robust power delivery network is hard to design. Moreover, limited by package design, decoupling capacitors cannot be flexibly put on package; only on-chip decoupling capacitors are available. Thus the power integrity becomes more serious. The study is divided into three parts. First, the best two-layer power-ground mesh layout design is proposed, which can reduce parasitic effects and improve power integrity. Second, the idea that reduces normalized resistance for better eye diagram is proposed. The table with the layout cross-sectional area versus the available longest distance is also given. Third, the signal interlacing layouts are suggested. Use two types of basic adjacent signal interlacing layout cells and the ghost leg algorithm to create any signal interlacing layout pattern in minimum distance and minimum level. Using our design suggestions contributes to the next generation wafer-level packaging technology development, gives design guidelines and increases the overall performance of the circuits.