- 學位論文
使用虛擬平衡信號於電源完整度之改善設計
Improvement of Power Integrity by Pseudo-Balanced Signaling
摘要
信號及電源完整度在高速數位傳輸系統中日趨重要，其完整性決定了信號的傳輸品質。由於數位系統操作頻率的增加，隨之而產生的同步切換雜訊限制了元件的工作表現。同步切換雜訊源自於電源供應網路中的寄生電感，如此將對電源及接地線造成電壓波動，進而降低雜訊邊限，限制了數位元件之最高傳輸頻率。平衡式信號傳輸法則藉由控制開啟的電晶體數目，使總驅動電流維持恆定，藉此減少電源供應網路電流之變動，因而降低同步切換雜訊。虛擬平衡電源傳輸線運用編碼方式將傳輸信號編碼成為平衡信號，同時降低額外的資料傳輸負擔，將可避免許多電晶體同時切換，降低同步切換雜訊因而改進信號傳輸品質。 本論文主要分兩部分，前半部提出最佳虛擬平衡方法減少額外的資料傳輸負擔，數值模擬結果驗證此方法對於電源層式及電源傳輸線式的微帶線印刷電路板能有效降低同步切換雜訊，提升信號眼圖之眼高表現。 接著本論文將虛擬平衡信號應用於工業界第三代雙倍資料率同步動態隨機存取記憶體（Double-Data-Rate Three Synchronous Dynamic Random Access Memory，一般稱為DDR3 SDRAM）之資料線(Data Line)傳輸，該電路板佈局為一控制器對二記憶體之兩層板架構，亦即上層板及下層板皆有信號線、電源線及地線之結構，模擬結果顯示，上述方法能有效降低同步切換雜訊，使傳輸信號品質提升。此外，本論文亦提出於上述記憶體電路板電源傳輸線上最佳去耦合電容擺放方式，提升可用頻寬，同時提出對於電源傳輸線式電源結構的去耦合電容最佳擺置流程設計。
並列摘要
Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. Pseudo-balanced power transmission line (PB-PTL) concept has been shown to reduce simultaneous switching noise and improve performance. This balanced signaling scheme minimizes the variation of the total driving current through the PDN by controlling the number of high and low states in the output data string. As the total driving current is maintained constant, the variation of the current can be minimized, and therefore SSN can be reduced. In this paper, the optimal pseudo-balanced scheme has been proposed for reducing the overhead. Numerical simulation results of power-plane-based and power-transmission-line-based microstrip PCB have demonstrated the validity of this optimal pseudo-balanced scheme for SSN reduction, resulting in better eye height and signal quality. Next, the pseudo-balanced scheme is employed to industrial double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM), which used one controller to control two DDR in a two-layer PCB with signal/power/ground coexisting in both layers. Simulation has shown that the pseudo-balanced scheme can reduce simultaneous switching noise to achieve better signal quality. Moreover, this thesis also proposes the optimal placement of decoupling capacitors on two-layer power trace structures to broaden usable bandwidth.