應用於工業主機板之DDR3記憶體訊號及電源完整度共模擬與分析

Signal and Power Integrity Co-Simulation and Analysis for DDR3 Memory on Industrial Platform PCBs

陳泳霖(Yong-Lin Chen)

指導教授 ： 吳瑞北

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.01290

摘要

本論文主要針對現今高速數位系統中，隨著工作時脈上升及資料傳輸率加快，訊號/電源完整度共模擬與分析是必要的，探討系統中的電磁效應及雜訊耦合機制，如何影響整個系統的訊號/電源完整度，藉由共模擬與分析，使系統達到性能最佳化。
在本論文中主要分為兩個部份，第一部份利用兩層板的耦合微帶線，探討訊號在上拉式(Pull Up)及下拉式(Pull Down)的訊號/電源完整度，分析電源傳輸線上的雜訊如何耦合至訊號傳輸線與電源傳輸線上的訊號如何擾動，而導致輸出訊號不正常響應。
接著針對實際工業主機板DDR記憶體系統進行訊號/電源完整度共模擬與分析。工業主機板上資料線(Data Line)的走線方式主要分為兩種：第一種為微帶線至微帶線，此走線方式為上層資料線經由連通柱(Via)穿到下層；第二種為微帶線至帶狀線，此為上層資料線經由連通柱穿到內層。根據此兩種走線方式探討時域響應及眼圖分析。本文另外提出了簡化且包含電路效應的輸入/輸出緩衝器模型(I/O Buffer Model)，將此緩衝器模型應用於DDR3資料線且考慮八個輸入/輸出緩衝器(1 Byte)同時切換對於眼圖的影響，相較於傳統的緩衝器模型，本文所提出緩衝器模型在模擬眼圖的上升/下降時間皆有改善，與示波器量測的結果非常接近，無論在眼高和眼寬都僅有5 %以內誤差，驗證了本文所提出輸入/輸出驅動電路模型的準確性。

關鍵字

訊號/電源完整度共模擬與分析 ； 輸入/輸出緩衝器模器 ； 耦合傳輸線 ； 工業主機板 ； 第三代雙倍資料率記憶體

並列摘要

With the clock and data rate increasing nowadays, the signal/power integrity co-simulation is necessary. The major theme of this thesis is to investigate how the electromagnetic effect and coupling mechanism affect the signal/power integrity of a whole system in recent high-speed-digital system. The achievement is to optimize the electrical performance of a system by co-simulating and analyzing.
There are two major parts in this thesis. First, the signal/power integrity will be researched as the signal is under pull up and pull down situations in two-layer coupled transmission line. The coupling mechanism of noise from power transmission line to signal transmission line and the fluctuation of power transmission line are analyzed, which lead to the abnormal waveform on signal.
Then, the integrity/power integrity co-simulation is analyzed on DDR memory bus on industrial PCB. There are two types of data line routing on industrial PCB: (i) microstrio to microstrip (ii) microstrip to strip-line. The time domain responses and eye-diagrams of these two types are investigated in this thesis. Besides, the simplified I/O buffer model with circuit consideration is also proposed in the thesis. Main contribution of proposed I/O buffer is to fully consider the capacitance effect of I/O circuit. Applying the proposed I/O buffer on DDR3 eight data lines (one byte) can obtain improved eye height and rising/falling time compared with conventional I/O buffer while eight data lines switch simultaneously. The simulation results using the proposed I/O buffer correlate with measurement results measured by oscilloscope. The error percentage is smaller than 5%, and shows the proposed I/O buffer is reliable and accurate.

並列關鍵字

Signal and power integrity co-simulation and analysis ； I/O buffer model ； Coupled transmission lines ； Industrial platform ； Double-Data-Rate three memory

參考文獻

[1] 呂信宏，工業電腦主機板高速訊號線訊號完整度分析與等化器設計，國立台灣大學碩士論文，2011年6月。

[7] 王佑甯，高速記憶體模組之信號完整度分析與補償設計，國立台灣大學碩士論文，2009年6月。

[5] R. Kollipara, S. Chang, C. Madden, H. Lan, L. Gopalakrishnan, S. Best, Y. Lu, S. Bangalore, G. E. Kumar, P. K. Venkatesan, K. Vyas, K. Prabhu, K. Kaviani, M. Bucher, and L. Luo, “Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system,” in IEEE Electro. Compon. Technol. Conf., Las Vagas, NV, May 28-31, 2013, pp. 1362–1371.

[6] S. Chaudhuri, J. A. McCall, and J. H. Salmon, “Proposal for BER based specifications for DDR4,” in Proc. IEEE 19th Topical Meeting Elect. Perform. Electro. Pakcage. Syst., Austin, TX, Oct. 25-27, 2010, pp. 121–124.

[8] E. Engin, W. John, G. Sommer, W. Mathis, and H. Reichl, “Modeling of striplines between a power and a ground plane,” IEEE Trans. Adv. Packag., vol. 29, no. 3, pp. 415–426, Aug. 2006.