具電感電流變異抑制技術之固定導通時間降壓轉換器

隨著物聯網與穿戴式裝備不斷的推陳出新，系統整合晶片(SOC)的需求也越來越大，在系統晶片中，每個子電路的規格不盡相同，主要為不同的供應電壓，為了滿足每個子電路的規格需求，電源供應晶片便顯得格外重要。而且在現今的應用中，電池為普遍的電源，故在滿足規格的同時，轉換效率也將會是一大考量，除此之外，電池電源有著電壓波動的問題，這個波動往往是隨著電池電量改變而產生的。本篇論文中對上述議題提出了一個電路架構在於電源管理給予討論以及改善。我們提出了一個電感電流壓抑的方法來抵抗電感電流的波動，本晶片操作在3MHz並且能壓抑幾乎全部的電流波動，同時達到91%以上的轉換效率。本電源管理晶片以TSMC 0.18µm CMOS製程實現，晶片面積為0.618毫米*0.995毫米。

關鍵字

電源管理晶片；降壓轉換器；電感電流

並列摘要

As the advance of mobile technology, the demand of System on Chip(SoC) is increasing. Many sub-circuits are needed in a single SoC, each sub-circuit has unique specification which means different supply voltages are needed. To satisfy these requirements, power management integrate circuits (PMICs) play an important part in a SoC. In this thesis, we propose a solution for power management which introduce an architecture that compensates the inductor current to against battery voltage variation which happens in all kinds of devices. To extend the lifetime of battery, which is widely used as power source in mobile device, efficiency and power consumption are also really important issues in circuit design. Our design can reach over 90% of power efficiency and suppress almost all the inductor ripple variation. This circuit is fabricated by TSMC 180nm CMOS technology. Chip area is 0.618mm x 0.995mm including bonding pad.

並列關鍵字

PMIC ； Buck ； Inductor ripple

參考文獻

[1] “Supporting the 6th Generation Intel® CoreTM Processor and intel® Xeon® Processor E3-1500 v5 Product Families based on the H-Platform” Intel, Inc.

Google Scholar

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/6th-gen-core-family-mobile-h-processor-lines-datasheet-vol-1.pdf

Google Scholar

[2] R. Gonzalez, B. M. Gordon and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," in IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug 1997.