高遷移率 n-型鍺錫金氧半場效電晶體之製作與分析

擁有高載子遷移率的鍺錫很有潛力成為下一代邏輯元件通道材料。當其中錫的比例超過 8–11% 時，鍺錫將會變成直接能隙，此時聚集在 Γ 能帶中的電子會增加，並降低電子的等效質量，提供高電子遷移率。然而，對於鍺錫 n-型元件的相關研究至今仍非常少，且其元件表現相較 p-型電晶體元件偏低，因此在本論文中，我們將針對高電子遷移率的 n-型電晶體元件進行研究。由於鍺錫在相對低溫即有可能會產生應變鬆弛或錫偏析的現象，我們首先製作矽基與鍺基元件，目的是為了最佳化製程步驟，減少製程中的熱預算。我們使用先閘極與後閘極製程製作元件並進行電性的分析比較，其中在矽基元件中，由於後閘極製程不須將閘極堆疊暴露在活化退火的高溫中，故此舉可以降低閘極漏電流；而在鍺基元件中，漏電流主要由 p-n 接面逆偏電流導致，後閘極製程並無法大幅改善元件漏電流。我們以先閘極製程製作鍺錫 n-型電晶體，藉由化學氣相沉積成長高品質鍺錫磊晶，並以離子佈植搭配快速升溫退火或微波退火製作源/汲極。在微波退火製作的元件中，漏電流能被有效的抑制，顯示微波退火作為低熱預算製程步驟的潛力。最後透過 I-V 與分離式 C-V 法，我們在微波退火製作的元件中萃取出了440 cm2/V·s 的高電子通道遷移率，表示低溫製程在鍺錫元件製程中的重要性。

關鍵字

鍺錫合金； n-型金氧半場效電晶體；電子遷移率

並列摘要

Germanium-tin (GeSn) with a high carrier mobility is a promising channel material for next-generation logic applications. GeSn alloys become direct bandgap as the Sn fraction is higher than 8–11%. The population of electrons in the Γ band will be increased and the effective electron mass will be reduced, enabling high-mobility device applications. However, only few works on GeSn nMOSFET devices have been reported and the devices were still underperformed. In this thesis, we focus on fabrication of high-mobility GeSn nMOSFETs. We first fabricated Si- and Ge-based n-FET devices to optimize the processing steps to reduce the thermal budgets for the GeSn fabrication since Sn segregation and strain relaxation occur at low temperatures. Gate-first and gate-last processes were done and compared. For Si devices, the gate leakage current can be effective suppressed by the gate-last process, which did not expose the gate stack to subsequent activation annealing steps. For Ge devices, there is no difference by those two processes since the dominant p-n junction leakage. GeSn n-MOSFETs were fabricated by the gate-first process. High quality strained GeSn films were epitaxially grown on Si substrates by the chemical vapor deposition. The source and drain regions were formed by ion implant and carriers were activated by rapid thermal annealing (RTA) or microwave annealing (MWA). By MWA, the device leakage can be effectively suppressed, showing the potential of the MWA step for the low-thermal budget process GeSn devices. The record-high mobility in the GeSn channel was extracted to be 440 cm2/V·s in the MWA-activated devices by I-V and split C-V characteristics. This suggests the low thermal budget processes of chemical vapor deposition and microwave annealing are crucial for the GeSn-based devices.

並列關鍵字

Germanium-tin (GeSn) ； nMOSFETs ； electron mobility

參考文獻

[1] R. Pillarisetty, “Academic and industry research progress in germanium nanodevices,” Nature, vol. 479, pp. 324–328, Nov. 2011.

[3] M. Liu, G. Han, Y. Liu, C. Zhang, H. Wang, X. Li, J. Zhang, B. Cheng, and Y. Hao, “Undoped Ge0.92Sn0.08 quantum well pMOSFETs on (001), (011) and (111) substrates with in situ Si2H6 passivation: High hole mobility and dependence of performance on orientation,” in Symposium on VLSI Technology, Jun. 2014, pp. 1–2.

[4] C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, “Activation and diffusion studies of ion-implanted p and n dopants in germanium,”

[5] C.-W. Chen, J.-Y. Tzeng, C.-T. Chung, H.-P. Chien, C.-H. Chien, and G.-L. Luo, “High-performance germanium p- and n-MOSFETs with NiGe source/drain,” IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2656–2661, Aug. 2014.

[6] M. Kobayashi, A. Kinoshita, K. Saraswat, H. S. P. Wong, and Y. Nishi, “Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge nMOSFET,” in Symposium on VLSI Technology, Jun. 2008, pp. 54–55.

國際替代計量

高遷移率 n-型鍺錫金氧半場效電晶體之製作與分析

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