本論文呈獻一個操作於5.12-GHz以LC振盪器之倍數延遲鎖定迴路為架構的分數型頻率合成器,此架構在長除數為128的狀況下仍可達到低雜訊效能。運用所提出的多工器在LC振盪器中,可將迴路頻寬由3-MHz增加至15-MHz (將近0.4倍參考頻率)且有抑制其中閃爍雜訊的效果。此外,此架構與再量化三角積分調變器的結合更可減少由於數位時間轉換器中的增益誤差所產生的突波量值和頻寬內雜訊。 這個提出的架構被實現於40nm CMOS工藝上,其主要面積為0.2平方毫米。在0.9伏特的電源供應下,其操作在5.12-GHz的抖動量 (被積分範圍從10-kHz到30-MHz)為177 fsrms (整數型)和326 fsrms (分數型),各自對應的功耗為1.81 mW和2.38mW,即便使用一個較低的40-MHz參考時脈。所提出的分數型頻率合成器在ㄧ個長除數頻率為128的狀況下,其質量因數 (figure-of-merit)最佳可達-252.5 dB (整數型)和-246 dB (分數型)。
This thesis presents a 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based multiplying delay-locked loop (MDLL) architecture which can achieve lower noise performance even with a large frequency multiplication factor (N) of 128. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3-MHz to 15-MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious tones and in-band noise, which come from the gain error of the digital-to-time converter (DTC). The proposed prototype has been fabricated in a 40 nm CMOS technology and occupies an area of 0.2 mm2. The integrated jitters, integrated from 10-kHz to 30-MHz, are 177 fsrms (integer-N) and 326 fsrms (fractional-N) with power consumption of 1.81 mW and 2.38 mW from a 0.9 V supply at 5.12-GHz respectively even with a lower reference clock of 40MHz. The figure-of-merit (FoMJ) of the proposed fractional-N frequency synthesizer can be as good as -252.5 dB (integer-N) and -246 dB (fractional-N) with a large frequency multiplication factor (N) of 128.