一個省面積且基於延遲鎖相迴路之除小數頻率合成器並利用在週期內重複使用延遲單元之方式實現

An Area-Efficient DLL-Based Fractional-N Frequency Synthesizer with Periodic Reuse of a Delay Cell Scheme

楊承學(Cheng-Shiue Yang)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201902130

摘要

本論文為一個省面積且基於延遲鎖相迴路之除小數頻率合成器並利用在週期內重複使用延遲單元之方式實現。現今常用的中央處理器和圖形處理器皆採用多個頻率合成器分別給不同核心單元獨立使用，針對不同核心的工作狀態，動態地調整時脈頻率來提供不同的輸出頻率，同時隨著製程的演進，單位面積的製程成本持續成長，因此頻率合成器的面積必須小型化，並且維持同樣的效能。
傳統常見的頻率合成器像是鎖相迴路，一般由相位比較器、電流幫浦、濾波器、振盪器、除頻器所構成。另一種實現方式是倍頻式延遲鎖相迴路，在倍頻的觀念上和鎖相迴路是大同小異的，但其有的特點是用每週期的參考時脈訊號重載於延遲線中去運作，相比鎖相迴路，參考時脈訊號就能夠直接的壓制頻率振盪器的雜訊，結果就會有較佳相位雜訊的表現。而有鑑於傳統的倍頻式延遲鎖相迴路往往需要很大的面積來實現高倍率的輸出頻率，所以在這裡我們提出了在週期內重複使用延遲單元之實現方式，以有效達到減少面積及高倍率輸出頻率的效果，同時也作到除小數的功能，使輸出頻率能有更高解析度的應用。
本晶片使用台積電90奈米互補式金氧半製程，主動區域面積約0.068mm2，在供應電源1.2V下，參考頻率為10MHz，輸出0.6GHz-0.8GHz的頻率範圍，參考突波達到-34dBc，從10kHz積分至10MHz的有效抖動值為7.319ps，在偏移輸出頻率1MHz的相位雜訊為-109.81dBc/Hz，消耗20.4mW功率。

關鍵字

除小數 ； 倍頻式延遲鎖相迴路 ； 相位雜訊 ； 元件重複使用 ； 省面積

並列摘要

An area efficient DLL-based fractional-N frequency synthesizer with cyclic reuse of a delay cell scheme is designed and implemented in the thesis. Nowadays, CPUs and GPUs adopt a number of frequency synthesizers for individual core in order to provide different frequencies by dynamically adjusting the operation frequency. Along with the progress in process, the cost per unit area keeps increasing. For that reason, the area of frequency synthesizer needs to be shrunk with the same performance.
There are two kinds of circuits in the conventional frequency synthesizers in general. One is the Phase-Locked Loop (PLL), composed of Phase Detector (PD), Charge Pump (CP), Loop Filter (LP), Voltage-Controlled Oscillator (VCO), Divider (DIV) generally. The other circuit to be realized is the Multiply Delay-Locked Loop (MDLL). Much as the concept of frequency multiplication is almost the same between PLL and MDLL, the characteristic in MDLL is that the reference clock in every cycle can be reloaded to operate in the delay line. The reference clock can suppress the noise from VCO to obtain the better performance of phase noise. The conventional MDLL also occupies lots of areas to achieve higher multiple ratio; as a result, we propose the cyclic reuse of a delay cell scheme. It not only shrinks the area to acquire higher multiple ratio but also achieves the function of fractional-N to make use of higher resolution’s application.
This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.068mm2 and 0.6GHz - 0.8GHz operation frequency. The reference spur is -34 dBc and the phase noise is -109.81 dBc/Hz at 1MHz offset from carrier frequency. The power dissipation under 1.2V supplying is 20.4mW.

並列關鍵字

Fractional-N ； MDLL ； Reusing Cells ； Area Efficient ； Phase Noise

參考文獻

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[2] Behzad Razavi, “Relation Between Delay Line Phase Noise and Oscillator Phase Noise.” IEEE Journal of Solid-State Circuits, 2014.

[3] P. Park, J. Park, and S.-H. Cho, “An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS.” IEEE Int. Solid-State Circuits Conference, 2012.

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[5] Wei Deng, “A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique,” IEEE Int. Solid-State Circuits Conference Dig. Tech. papers, Feb. 2015.